Generate HDL test bench from model or subsystem
makehdltb( generates
an HDL test bench from the specified subsystem or model reference.dut)
If you have not previously executed makehdl within
the current MATLAB® session, makehdltb calls makehdl to
generate model code before generating the test bench code. Properties
passed in to makehdl persist after makehdl executes,
and (unless explicitly overridden) are passed to subsequent makehdl calls
during the same MATLAB session.
makehdltb( generates
an HDL test bench from the specified subsystem or model reference
with options specified by one or more name-value pair arguments.dut,Name,Value)
Generate VHDL® DUT and test bench for a subsystem.
Use makehdl to generate VHDL code
for the subsystem symmetric_fir.
makehdl('sfir_fixed/symmetric_fir')### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Starting HDL check.
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings,
and 0 messages.
### Begin VHDL Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as
hdlsrc\sfir_fixed\symmetric_fir.vhd
### HDL code generation complete.After makehdl is complete, use makehdltb to
generate a VHDL test bench for the same subsystem.
makehdltb('sfir_fixed/symmetric_fir')### Begin TestBench generation. ### Generating HDL TestBench for 'sfir_fixed/symmetric_fir'. ### Begin simulation of the model 'gm_sfir_fixed'... ### Collecting data... ### Generating test bench: hdlsrc\sfir_fixed\symmetric_fir_tb.vhd ### Creating stimulus vectors... ### HDL TestBench generation complete.
hdlsrc folder.Generate Verilog® DUT and test bench for a subsystem.
Use makehdl to generate Verilog code
for the subsystem symmetric_fir.
makehdl('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')
### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Starting HDL check.
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings,
and 0 messages.
### Begin Verilog Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as
hdlsrc\sfir_fixed\symmetric_fir.v
### HDL code generation complete.After makehdl is complete, use makehdltb to
generate a Verilog test bench for the same subsystem.
makehdltb('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')
### Begin TestBench generation. ### Generating HDL TestBench for 'sfir_fixed/symmetric_fir'. ### Begin simulation of the model 'gm_sfir_fixed'... ### Collecting data... ### Generating test bench: hdlsrc\sfir_fixed\symmetric_fir_tb.v ### Creating stimulus vectors... ### HDL TestBench generation complete.
hdlsrc\sfir_fixed folder.Generate SystemVerilog DPI test bench for a subsystem.
Consider this option if generation or simulation of the default
HDL test bench takes a long time. Generation of a DPI test bench can
be faster than the default version because it does not run a Simulink® simulation
to create the test bench data. Simulation of a DPI test bench with
a large data set is faster than the default version because it does
not store the input or expected data in a separate file. For requirements
to use this feature, see the GenerateSVDPITestBench property.
Use makehdl to generate Verilog code
for the subsystem symmetric_fir.
makehdl('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')
### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Starting HDL check.
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings,
and 0 messages.
### Begin Verilog Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as
hdlsrc\sfir_fixed\symmetric_fir.v
### HDL code generation complete.After the code is generated, use makehdltb to
generate a test bench for the same subsystem. Specify your HDL simulator
so that the coder can generate scripts to build and run the generated
SystemVerilog and C code. Disable generation of the default test bench.
makehdltb('sfir_fixed/symmetric_fir','TargetLanguage','Verilog',... 'GenerateSVDPITestBench','ModelSim','GenerateHDLTestBench','off')
### Start checking model compatibility with SystemVerilog DPI testbench ### Finished checking model compatibility with SystemVerilog DPI testbench ### Preparing generated model for SystemVerilog DPI component generation ### Generating SystemVerilog DPI component ### Starting build procedure for model: gm_sfir_fixed_ref ### Starting SystemVerilog DPI Component Generation ### Generating DPI H Wrapper gm_sfir_fixed_ref_dpi.h ### Generating DPI C Wrapper gm_sfir_fixed_ref_dpi.c ### Generating SystemVerilog module gm_sfir_fixed_ref_dpi.sv using template C:\matlab\toolbox\hdlverifier\dpigenerator\rtw\hdlverifier_dpitb_template.vgt ### Generating makefiles for: gm_sfir_fixed_ref_dpi ### Invoking make to build the DPI Shared Library ### Successful completion of build procedure for model: gm_sfir_fixed_ref ### Working on symmetric_fir_dpi_tb as hdlsrc\sfir_fixed\symmetric_fir_dpi_tb.sv. ### Generating SystemVerilog DPI testbench simulation script for ModelSim/QuestaSim hdlsrc\sfir_fixed\symmetric_fir_dpi_tb.do ### HDL TestBench generation complete.
hdlsrc\sfir_fixed folder.dut — DUT subsystem or model reference nameDUT subsystem or model reference name, specified as a character vector, with full hierarchical path.
Example: 'modelname/subsysTarget'
Example: 'modelname/subsysA/subsysB/subsysTarget'
Specify optional
comma-separated pairs of Name,Value arguments. Name is
the argument name and Value is the corresponding value.
Name must appear inside quotes. You can specify several name and value
pair arguments in any order as
Name1,Value1,...,NameN,ValueN.
'TargetLanguage','Verilog''TargetLanguage' — Target language'VHDL' (default) | 'Verilog'Specify whether to generate VHDL or Verilog code. For more information, see the Language section in Target.
'TargetDirectory' — Output directory'hdlsrc' (default) | character vectorSpecify a path to write the generated files and HDL code into. For more information, see the Folder section in Target.
'SplitEntityArch' — Split VHDL entity and architecture into separate files'off' (default) | 'on'For more information, see Split entity and architecture in Split entity and architecture.
'GenerateHDLTestBench' — Generate HDL test bench'on' (default) | 'off'The coder generates an HDL test bench by running a Simulink simulation to capture input vectors and expected output data for your DUT. For more information, see HDL test benchTest Bench Generation Output.
'GenerateSVDPITestBench' — Generate SystemVerilog DPI test bench'none' (default) | 'ModelSim' | 'Incisive' | 'VCS' | 'Vivado Simulator'When you set this property, the coder generates a direct programming interface (DPI) component for your entire Simulink model, including your DUT and data sources. Your entire model must support C code generation with Simulink Coder™. The coder generates a SystemVerilog test bench that compares the output of the DPI component with the output of the HDL implementation of your DUT. The coder also builds shared libraries and generates a simulation script for the simulator you select.
Consider using this option if the default HDL test bench takes a long time to generate or simulate. Generation of a DPI test bench is sometimes faster than the default version because it does not run a full Simulink simulation to create the test bench data. Simulation of a DPI test bench with a large data set is faster than the default version because it does not store the input or expected data in a separate file. For an example, see Generate a SystemVerilog DPI Test Bench.
To use this feature, you must have HDL Verifier™ and Simulink Coder licenses. To run the SystemVerilog testbench with generated VHDL code, you must have a mixed-language simulation license for your HDL simulator.
This test bench is not supported when you generate HDL code for the top-level Simulink model. Your DUT subsystem must meet the following conditions:
Input and output data types of the DUT cannot be larger than 64 bits.
Input and output ports of the DUT cannot use enumerated data types.
Input and output ports cannot be single-precision or double-precision data types.
The DUT cannot have multiple clocks. You must set
the Clock inputs code generation option to Single.
Use trigger signal as clock must not be selected.
If the DUT uses vector ports, you must use Scalarize vector ports to flatten the interface.
'GenerateCoSimBlock' — Generate HDL Cosimulation block'off' (default) | 'on'Generate an HDL Cosimulation block so you can simulate the DUT in Simulink with an HDL simulator.
For more information, see GenerateCoSimBlock.
'GenerateCoSimModel' — Generate HDL Cosimulation model'ModelSim' (default) | 'Incisive' | 'None'Generate a model containing an HDL Cosimulation block for the specified HDL simulator.
For more information, see GenerateCoSimModel.
'HDLCodeCoverage' — Enable code coverage on the generated test bench'off' (default) | 'on'Include code coverage switches in the generated build-and-run
scripts. These switches turn on code coverage for the generated test
bench. Specify your HDL simulator in the SimulationTool property.
The coder generates build-and-run scripts for the simulator you specify.
'SimulationTool' — HDL simulator where you will run the generated test bench'ModelSim' (default) | 'Incisive' | 'VCS' | 'Vivado' | 'Custom'This property applies to generated test benches. 'VCS' and 'Vivado' are
supported only for SystemVerilog DPI test benches. When you select 'Custom',
the tool uses the custom script settings. See the “Script Generation”
properties.
'ForceClock' — Force clock input'on' (default) | 'off'Specify that the generated test bench drives the clock enable
input based on ClockLowTime and ClockHighTime.
For more information, see ForceClock.
'ClockHighTime' — Clock high timeClock high time during a clock period, specified in nanoseconds.
For more information, see ClockHighTime.
'ClockLowTime' — Clock low timeClock low time during a clock period, specified in nanoseconds.
For more information, see ClockLowTime.
'ForceClockEnable' — Force clock enable input'on' (default) | 'off'Specify that the generated test bench drives the clock enable input.
For more information, see ForceClockEnable.
'ClockInputs' — Single or multiple clock inputs'Single' (default) | 'Multiple'Specify whether to generate single or multiple clock inputs in the HDL code. For more information, see the Clock inputs section in Clock Settings and Timing Controller Postfix.
'ForceReset' — Force reset input'on' (default) | 'off'Specify that the generated test bench drives the reset input.
For more information, see ForceReset.
'ResetLength' — Reset asserted time lengthLength of time that reset is asserted, specified as the number of clock cycles.
For more information, see Reset length in Clock Enable and Reset Input Signals.
'ResetAssertedLevel' — Asserted (active) level of reset'active-high' (default) | 'active-low'Specify whether to use an active-high or active-low asserted level for the reset input signal. For more information, see the Reset asserted level section in Reset Settings.
'HoldInputDataBetweenSamples' — Hold valid data for signals clocked at slower rate'on' (default) | 'off'For more information, see HoldInputDataBetweenSamples.
'HoldTime' — Hold time for inputs and forced resetHold time for inputs and forced reset, specified in nanoseconds.
For more information, see HoldTime.
'IgnoreDataChecking' — Time to wait after clock enable before checking output dataTime after clock enable is asserted before starting output data checks, specified in number of samples.
For more information, see IgnoreDataChecking.
'InitializeTestBenchInputs' — Initialize test bench inputs to 0'off' (default) | 'on'For more information, see InitializeTestBenchInputs.
'MultifileTestBench' — Divide generated test bench into helper functions, data, and HDL test bench files'off' (default) | 'on'For more information, see MultifileTestBench.
'UseFileIOInTestBench' — Use file I/O to read/write test bench data'on' (default) | 'off'For more information, see UseFileIOInTestBench.
'TestBenchClockEnableDelay' — Number of clock cycles between deassertion of reset and assertion of clock enableFor more information, see TestBenchClockEnableDelay.
'TestBenchDataPostFix' — Postfix for test bench data file name'_data' (default) | character vectorFor more information, see TestBenchDataPostFix.
'TestBenchPostFix' — Suffix for test bench name'_tb' (default) | character vectorFor more information, see TestBenchPostFix.
'UseVerilogTimescale' — Generate 'timescale compiler directives'on' (default) | 'off'For more information, see Use Verilog 'timescale directives in RTL Annotations.
'DateComment' — Include time stamp in header'on' (default) | 'off'For more information, see Emit time/date stamp in header in RTL Annotations.
'InlineConfigurations' — Include VHDL configurations'on' (default) | 'off'For more information, see Inline VHDL configuration in RTL Annotations.
'ScalarizePorts' — Flatten vector ports into scalar ports'off' (default) | 'on'For more information, see Scalarize vector ports in RTL Style.
'HDLCompileInit' — Compilation script initialization text'vlib %s\n' (default) | character vectorFor more information, see HDLCompileInit.
'HDLCompileTerm' — Compilation script termination text'' (default) | character vectorFor more information, see HDLCompileTerm.
'HDLCompileFilePostfix' — Postfix for compilation script file name'_compile.do' (default) | character vectorFor more information, see HDLCompileFilePostfix.
'HDLCompileVerilogCmd' — Verilog compilation command'vlog %s %s\n' (default) | character vectorVerilog compilation command, specified as a character vector.
The SimulatorFlags name-value pair specifies the
first argument, and the module name specifies the second argument.
For more information, see HDLCompileVerilogCmd.
'HDLCompileVHDLCmd' — VHDL compilation command'vcom %s %s\n' (default) | character vectorVHDL compilation command, specified as a character vector.
The SimulatorFlags name-value pair specifies the
first argument, and the entity name specifies the second argument.
For more information, see HDLCompileVHDLCmd.
'HDLSimCmd' — HDL simulation command'vsim -novopt %s.%s\n' (default) | character vectorThe HDL simulation command, specified as a character vector.
For more information, see HDLSimCmd.
'HDLSimInit' — HDL simulation script initialization name['onbreak resume\n', 'onerror resume\n'] (default) | character vectorInitialization for the HDL simulation script, specified as a character vector.
For more information, see HDLSimInit.
'HDLSimTerm' — HDL simulation script termination name'run -all' (default) | character vectorThe termination name for the HDL simulation command, specified as a character vector.
For more information, see HDLSimTerm.
'HDLSimFilePostfix' — Postscript for HDL simulation script'_sim.do' (default) | character vectorFor more information, see HDLSimFilePostfix.
'HDLSimViewWaveCmd' — HDL simulation waveform viewing command'add wave sim:%s\n' (default) | character vectorWaveform viewing command, specified as a character vector. The implicit argument adds the signal paths for the DUT top-level input, output, and output reference signals.
For more information, see HDLSimViewWaveCmd.
'ClockEnableInputPort' — Clock enable input port name'clk_enable' (default) | character vectorSpecify the clock enable input port name as a character vector. For more information, see Clock Enable Settings.
'ClockEnableOutputPort' — Clock enable output port name'ce_out' (default) | character vectorClock enable output port name, specified as a character vector.
For more information, see Clock Enable output port.
'ClockInputPort' — Clock input port name'clk' (default) | character vectorSpecify the clock input port name as a character vector. For more information, see Clock Settings and Timing Controller Postfix.
'ResetInputPort' — Reset input port name'reset' (default) | character vectorReset input port name, specified as a character vector.
For more information, see the Reset input port section in Reset Settings.
'VerilogFileExtension' — Verilog file extension'.v' (default) | character vectorSpecify the file name extension for generated Verilog files. For more information, see Language-Specific Identifiers.
'VHDLFileExtension' — VHDL file extension'.vhd' (default) | character vectorSpecify the file name extension for generated VHDL files. For more information, see the VHDLFileExtension section in Language-Specific Identifiers.
'VHDLArchitectureName' — VHDL architecture name'rtl' (default) | character vectorFor more information, see VHDL architecture name in VHDL Architecture and Library Name.
'VHDLLibraryName' — VHDL library name'work' (default) | character vectorFor more information, see VHDL library name in VHDL Architecture and Library Name.
'SplitEntityFilePostfix' — Postfix for VHDL entity file names'_entity' (default) | character vectorFor more information, see Split entity file postfix in Split entity and architecture.
'SplitArchFilePostfix' — Postfix for VHDL architecture file names'_arch' (default) | character vectorFor more information, see Split arch file postfix in Split entity and architecture.
'PackagePostfix' — Postfix for package file name'_pkg' (default) | character vectorSpecify the postfix for the package file name as a character vector. For more information, see the Package Postfix section in Language-Specific Identifiers.
'ComplexImagPostfix' — Postfix for imaginary part of complex signal'_im' (default) | character vectorFor more information, see Complex imaginary part postfix in Complex Signals Postfix.
'ComplexRealPostfix' — Postfix for imaginary part of complex signal names'_re' (default) | character vectorFor more information, see Complex real part postfix in Complex Signals Postfix.
'EnablePrefix' — Prefix for internal enable signals'enb' (default) | character vectorPrefix for internal clock enable and control flow enable signals, specified as a character vector. For more information, see Clock Enable Settings.