Specify period, in nanoseconds, during which test bench drives clock input signals high (1)
ns
Default: 5
The clock high time is expressed as a positive integer.
The ClockHighTime and ClockLowTime properties
define the period and duty cycle for the clock signal. Using the defaults, the clock signal
is a square wave (50% duty cycle) with a period of 10 ns.
HDL Coder™ ignores this
property if ForceClock is set to off.
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
ClockLowTime, ForceClock, ForceClockEnable, ForceReset, HoldTime