makehdl
Generate HDL RTL code from model, subsystem, or model reference
Description
makehdl( generates HDL code from the specified
DUT model, subsystem, or model reference.dut)
Note
Running this command can activate the Open at simulation start setting for blocks such as the Scope block and therefore invoke the block.
makehdl( generates
HDL code from the specified DUT model, subsystem, or model reference
with options specified by one or more name-value pair arguments.dut,Name,Value)
Examples
Generate VHDL for the Current Model
This example shows how to generate VHDL for the symmetric FIR model.
Open the sfir_fixed model.
sfir_fixed
Generate HDL code for the current model with code generation options set to default values.
makehdl('sfir_fixed/symmetric_fir','TargetDirectory','C:\GenVHDL\hdlsrc')
### Generating HDL for 'sfir_fixed/symmetric_fir'. ### Starting HDL check. ### Begin VHDL Code Generation for 'sfir_fixed'. ### Working on sfir_fixed/symmetric_fir as C:\GenVHDL\hdlsrc\sfir_fixed\symmetric_fir.vhd. ### Creating HDL Code Generation Check Report file://C:\GenVHDL\hdlsrc\sfir_fixed\symmetric_fir_report.html ### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages. ### HDL code generation complete.
The generated VHDL code is saved in the hdlsrc folder.
Generate Verilog for a Subsystem Within a Model
Generate Verilog® for the subsystem symmetric_fir within the model sfir_fixed.
Open the sfir_fixed model.
sfir_fixed;
The model opens in a new Simulink® window.
Generate Verilog for the symmetric_fir subsystem.
makehdl('sfir_fixed/symmetric_fir', 'TargetLanguage', 'Verilog', ... 'TargetDirectory', 'C:/Generate_Verilog/hdlsrc')
### Generating HDL for 'sfir_fixed/symmetric_fir'. ### Starting HDL check. ### Begin Verilog Code Generation for 'sfir_fixed'. ### Working on sfir_fixed/symmetric_fir as C:\Generate_Verilog\hdlsrc\sfir_fixed\symmetric_fir.v. ### Creating HDL Code Generation Check Report file://C:\Generate_Verilog\hdlsrc\sfir_fixed\symmetric_fir_report.html ### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages. ### HDL code generation complete.
The generated Verilog code for the symmetric_fir subsystem is saved in hdlsrc\sfir_fixed\symmetric_fir.v.
Close the model.
bdclose('sfir_fixed');
Check Subsystem for Compatibility with HDL Code Generation
Check that the subsystem symmetric_fir is compatible with HDL code generation, then generate HDL.
Open the sfir_fixed model.
sfir_fixed
The model opens in a new Simulink® window.
Use the checkhdl function to check whether the symmetric_fir subsystem is compatible with HDL code generation.
hdlset_param('sfir_fixed','TargetDirectory','C:/HDL_Checks/hdlsrc'); checkhdl('sfir_fixed/symmetric_fir')
### Starting HDL check. ### Creating HDL Code Generation Check Report file://C:\HDL_Checks\hdlsrc\sfir_fixed\symmetric_fir_report.html ### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages.
checkhdl completed successfully, which means that the model is compatible for HDL code generation. To generate code, use makehdl
makehdl('sfir_fixed/symmetric_fir')
### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Using the config set for model <a href="matlab:configset.showParameterGroup('sfir_fixed', { 'HDL Code Generation' } )">sfir_fixed</a> for HDL code generation parameters.
### Starting HDL check.
### Begin VHDL Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as C:\HDL_Checks\hdlsrc\sfir_fixed\symmetric_fir.vhd.
### Creating HDL Code Generation Check Report file://C:\HDL_Checks\hdlsrc\sfir_fixed\symmetric_fir_report.html
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.
The generated VHDL® code for the symmetric_fir subsystem is saved in hdlsrc\sfir_fixed\symmetric_fir.vhd.
Close the model.
bdclose('sfir_fixed');
Input Arguments
dut — DUT model or subsystem name
character vector
Specified as subsystem name, top-level model name, or model reference name with full hierarchical path.
Example: 'top_level_name'
Example: 'top_level_name/subsysA/subsysB/codegen_subsys_name'
Name-Value Pair Arguments
Specify optional
comma-separated pairs of Name,Value arguments. Name is
the argument name and Value is the corresponding value.
Name must appear inside quotes. You can specify several name and value
pair arguments in any order as
Name1,Value1,...,NameN,ValueN.
'TargetLanguage','Verilog'Target Options
'HDLSubsystem' — DUT Subsystem
character vector
Specify the Subsystem in your model to generate HDL code for. For more information, see the Generate HDL for section in Target.
'TargetLanguage' — Target language
'VHDL' (default) | 'Verilog'
Specify whether to generate VHDL or Verilog code. For more information, see the Language section in Target.
'TargetDirectory' — Output directory
'hdlsrc' (default) | character vector
Specify a path to write the generated files and HDL code into. For more information, see the Folder section in Target.
'SplitEntityArch' — Split VHDL® entity and architecture into separate files
'off' (default) | 'on'
For more information, see Split entity and architecture in Split entity and architecture.
'UseSingleLibrary' — Generate VHDL code for model references into a single library
'off' (default) | 'on'
For more information, see Generate VHDL code for model references into a single library.
Code Generation Output Options
'CodeGenerationOutput' — Generation of HDL code and display of generated model
'GenerateHDLCode' (default) | 'GenerateHDLCodeAndDisplayGeneratedModel' | 'DisplayGeneratedModelOnly'
Specify whether you want to generate HDL code, or only display the generated model, or generate HDL code and display the generated model. For more information, see the Generate HDL code section in Code Generation Output.
'GenerateHDLCode' — Generate HDL code
'on' (default) | 'off'
Specify whether to generate HDL code for the model. For more information, see the Generate HDL code section in Code Generation Output.
'GenerateValidationModel' — Generate validation model
'off' (default) | 'on'
Specify whether to generate the validation model with HDL code. For more information, see the Generate validation model section in Code Generation Output.
Code Generation Report Options
'HDLCodingStandard' — Specify HDL coding standard
character vector
Specify whether the generated HDL code must conform to the Industry coding standard guidelines. For more information, see Choose Coding Standard and Report Options.
'HDLCodingStandardCustomizations' — Specify HDL coding standard customization object
hdlcoder.CodingStandard object
Specify the coding standards customization object to use with the
Industry coding standard when generating HDL code. For more information,
see hdlcoder.CodingStandard.
'Traceability' — Generate report with mapping links between HDL and model
'off' (default) | 'on'
Specify whether to generate a traceability report that has hyperlinks for navigating from code-to-model and from model-to-code. For more information, see Generate traceability report.
'ResourceReport' — Resource utilization report generation
'off' (default) | 'on'
Specify whether to generate a resource utilization report that displays the number of hardware resources that the generated HDL code uses. For more information, see Generate resource utilization report.
'OptimizationReport' — Optimization report generation
'off' (default) | 'on'
Specify whether to generate an optimization report that displays the effect of optimizations such as streaming, sharing, and distributed pipelining. For more information, see Generate optimization report.
'HDLGenerateWebview' — Include model Web view
'on' (default) | 'off'
Specify whether to generate a web view of the model in the Code Generation report to easily navigate between the code and model. For more information, see Generate model Web view.
Speed and Area Optimization
'BalanceDelays' — Delay balancing
'on' (default) | 'off'
Specify whether to enable delay balancing on the model. For more information, see Balance delays.
'DistributedPipeliningPriority' — Specify priority for distributed pipelining algorithm
'NumericalIntegrity' (default) | 'Performance'
Specify whether to prioritize the distributed pipelining optimization for numerical integrity or performance. For more information, see the Distributed pipelining priority section in Distributed Pipelining.
'HierarchicalDistPipelining' — Hierarchical distributed pipelining
'off' (default) | 'on'
Specify whether to apply the hierarchical distributed pipelining optimization on the model. For more information, see Distributed Pipelining.
'PreserveDesignDelays' — Prevent distributed pipelining from moving design delays
'off' (default) | 'on'
Specify whether you want the code generator to distribute design delays in your model. For more information, see Preserve design delays.
'ClockRatePipelining' — Insert pipeline registers at the clock rate instead of the data rate for multi-cycle paths
'on' (default) | 'off'
Specify whether to insert pipeline registers at the clock rate or the data rate. For more information, see Clock Rate Pipelining.
'MinimizeClockEnables' — Omit clock enable logic for single-rate designs
'off' (default) | 'on'
For more information, see Minimize Clock Enables and Reset Signals.
'RAMMappingThreshold' — Minimum RAM size for mapping to RAMs instead of registers
256 (default) | positive integer
Specify, in bits, the minimum RAM size required for mapping to RAMs instead of registers. For more information, see the RAM mapping threshold (bits) section in RAM Mapping.
'MapPipelineDelaysToRAM' — Map pipeline registers in the generated HDL code to RAM
'off' (default) | 'on'
Specify whether to map pipeline registers in the generated HDL code to block RAMs on the FPGA. For more information, see the Map pipeline delays to RAM section in RAM Mapping.
'HighlightFeedbackLoops' — Highlight feedback loops inhibiting delay balancing and optimizations
'off' (default) | 'on'
Specify whether to highlight feedback loops in your design. For more information, see Diagnostics for Optimizations.
Coding Style
'UserComment' — HDL file header comment
character vector
Specify comment lines in header of generated HDL and test bench files. For more information, see Comment in header.
'UseAggregatesForConst' — Represent constant values with aggregates
'off' (default) | 'on'
For more information, see Represent constant values by aggregates in RTL Customizations for Constants and MATLAB Function Blocks.
'UseRisingEdge' — Use VHDL rising_edge or falling_edge function
to detect clock transitions
'off' (default) | 'on'
For more information, see Use "rising_edge/falling_edge" style for registers in RTL Style.
'LoopUnrolling' — Unroll VHDL FOR and GENERATE loops
'off' (default) | 'on'
For more information, see Loop unrolling in RTL Style.
'UseVerilogTimescale' — Generate 'timescale compiler directives
'on' (default) | 'off'
For more information, see Use Verilog 'timescale directives in RTL Annotations.
'InlineConfigurations' — Include VHDL configurations
'on' (default) | 'off'
For more information, see Inline VHDL configuration in RTL Annotations.
'SafeZeroConcat' — Type-safe syntax for concatenated zeros
'on' (default) | 'off'
For more information, see Concatenate type safe zeros in RTL Annotations.
'ObfuscateGeneratedHDLCode' — Obfuscate generated HDL code
'off' (default) | 'on'
Specify whether you want to obfuscate the generated HDL code. For more information, see Generate obfuscated HDL code in RTL Annotations.
'DateComment' — Include time stamp in header
'on' (default) | 'off'
For more information, see Emit time/date stamp in header in RTL Annotations.
'ScalarizePorts' — Flatten vector ports into scalar ports
'off' (default) | 'on'
For more information, see Scalarize vector ports in RTL Style.
'MinimizeIntermediateSignals' — Minimize intermediate signals
'off' (default) | 'on'
For more information, see Minimize intermediate signals in RTL Style.
'RequirementComments' — Link from code generation reports to requirement documents
'on' (default) | 'off'
For more information, see Include requirements in block comments in RTL Annotations.
'InlineMATLABBlockCode' — Inline HDL code for MATLAB Function blocks
'off' (default) | 'on'
For more information, see Inline MATLAB Function block code RTL Customizations for Constants and MATLAB Function Blocks.
'MaskParameterAsGeneric' — Reusable code generation for subsystems with identical mask parameters
'off' (default) | 'on'
For more information, see Generate parameterized HDL code from masked subsystem in RTL Style.
'InitializeBlockRAM' — Initial signal value generation for RAM blocks
'on' (default) | 'off'
For more information, see Initialize all RAM blocks in RTL Customizations for RAMs.
'RAMArchitecture' — RAM architecture
'WithClockEnable' (default) | 'WithoutClockEnable'
For more information, see RAM Architecture in RTL Customizations for RAMs.
Clocks and Reset
'ClockEdge' — Active clock edge
'Rising' (default) | 'Falling'
Specify the active clock edge for the generated HDL code. For more information, see the Clock edge section in Clock Settings and Timing Controller Postfix.
'ClockInputs' — Single or multiple clock inputs
'Single' (default) | 'Multiple'
Specify whether to generate single or multiple clock inputs in the HDL code. For more information, see the Clock inputs section in Clock Settings and Timing Controller Postfix.
'Oversampling' — Oversampling factor for global clock
1 (default) | integer greater than or equal to 0
Frequency of global oversampling clock, specified as an integer multiple of the model’s base rate. For more information, see Oversampling factor.
'ResetAssertedLevel' — Asserted (active) level of reset
'active-high' (default) | 'active-low'
Specify whether to use an active-high or active-low asserted level for the reset input signal. For more information, see the Reset asserted level section in Reset Settings.
'ResetType' — Reset type
'async' (default) | 'sync'
Specify whether to use synchronous or asynchronous reset in the generated HDL code. For more information, see Reset Settings.
'TriggerAsClock' — Use trigger signal as clock in triggered subsystems
'off' (default) | 'on'
For more information, see Use trigger signal as clock.
'TimingControllerArch' — Generate reset for timing controller
'default' (default) | 'resettable'
For more information, see Timing controller architecture in Timing Controller Settings.
Test Bench
'GenerateCoSimBlock' — Generate HDL Cosimulation block
'off' (default) | 'on'
When you use this property with makehdl,
HDL Coder™ does not a Cosimulation block. To generate a Cosimulation
block, use makehdltb. With the Cosimulation block,
you can simulate the DUT in Simulink® with an HDL simulator.
For more information, see GenerateCoSimBlock.
'GenerateCoSimModel' — Generate HDL Cosimulation Model
'ModelSim' (default) | 'Incisive' | 'None'
When you use this property with makehdl,
HDL Coder does not a Cosimulation model. To generate a Cosimulation
model, use makehdltb. The model contains a
Cosimulation block for the HDL simulator that you specify.
For more information, see GenerateCoSimModel.
'SimulatorFlags' — Options for generated compilation scripts
character vector
For more information, see SimulatorFlags.
'TestBenchReferencePostFix' — Suffix for test bench reference signals
'_ref' (default) | character vector
For more information, see TestBenchReferencePostFix.
Script Generation
'EDAScriptGeneration' — Enable or disable script generation for third-party tools
'on' (default) | 'off'
For more information, see EDAScriptGeneration.
'HDLCompileInit' — Compilation script initialization text
'vlib %s\n' (default) | character vector
For more information, see HDLCompileInit.
'HDLCompileTerm' — Compilation script termination text
'' (default) | character vector
For more information, see HDLCompileTerm.
'HDLCompileFilePostfix' — Postfix for compilation script file name
'_compile.do' (default) | character vector
For more information, see HDLCompileFilePostfix.
'HDLCompileVerilogCmd' — Verilog® compilation command
'vlog %s %s\n' (default) | character vector
Verilog compilation command, specified as a character vector.
The SimulatorFlags name-value pair specifies the
first argument, and the module name specifies the second argument.
For more information, see HDLCompileVerilogCmd.
'HDLCompileVHDLCmd' — VHDL compilation command
'vcom %s %s\n' (default) | character vector
VHDL compilation command, specified as a character vector.
The SimulatorFlags name-value pair specifies the
first argument, and the entity name specifies the second argument.
For more information, see HDLCompileVHDLCmd.
'HDLLintTool' — HDL lint tool
'None' (default) | 'AscentLint' | 'Leda' | 'SpyGlass' | 'Custom'
For more information, see HDLLintTool.
'HDLLintInit' — HDL lint initialization name
character vector
HDL lint initialization name, specified as a character vector. The
default is derived from the HDLLintTool name-value
pair.
For more information, see HDLLintInit.
'HDLLintCmd' — HDL lint command
character vector
HDL lint command, specified as a character vector. The default is
derived from the HDLLintTool name-value pair.
For more information, see HDLLintCmd.
'HDLLintTerm' — HDL lint termination name
character vector
HDL lint termination, specified as a character vector. The default is
derived from the HDLLintTool name-value pair.
For more information, see HDLLintTerm.
'HDLSynthTool' — Synthesis tool
'None' (default) | 'ISE' | 'Libero' | 'Precision' | 'Quartus' | 'Synplify' | 'Vivado' | 'Custom'
For more information, see HDLSynthTool.
'HDLSynthCmd' — HDL synthesis command
character vector
HDL synthesis command, specified as a character vector. The default is
derived from the HDLSynthTool name-value pair.
For more information, see HDLSynthCmd.
'HDLSynthFilePostfix' — Postfix for synthesis script file name
character vector
HDL synthesis script file name postfix, specified as a character
vector. The default is derived from the HDLSynthTool
name-value pair.
For more information, see HDLSynthFilePostfix.
'HDLSynthInit' — Synthesis script initialization name
character vector
Initialization for the HDL synthesis script, specified as a character
vector. The default is derived from the HDLSynthTool
name-value pair.
For more information, see HDLSynthInit.
'HDLSynthTerm' — Synthesis script termination name
character vector
Termination name for the HDL synthesis script. The default is derived
from the HDLSynthTool name-value pair.
For more information, see HDLSynthTerm.
Generated Model
'GeneratedModelNamePrefix' — Prefix for generated model name
'gm_' (default) | character vector
For more information, see Prefix for generated model name.
Synthesis
'SynthesisTool' — Synthesis tool
'' (default) | 'Altera Quartus II' | 'Xilinx ISE' | 'Xilinx Vivado'
Specify the synthesis tool for targeting the generated HDL code as a character vector. For more information, see Tool and Device.
'SynthesisToolChipFamily' — Synthesis tool chip family
'' (default) | character vector
Specify the synthesis tool chip family for the target device as a character vector. For more information, see the Family section in Tool and Device.
'SynthesisToolDeviceName' — Synthesis tool device name
'' (default) | character vector
Specify the synthesis tool device name for the target device as a character vector. For more information, see the Device section in Tool and Device.
'SynthesisToolPackageName' — Synthesis tool package name
'' (default) | character vector
Specify the synthesis tool package name for the target device as a character vector. For more information, see the Package section in Tool and Device.
'SynthesisToolSpeedValue' — Synthesis tool speed value
'' (default) | character vector
Specify the synthesis tool speed value for the target device as a character vector. For more information, see the Speed section in Tool and Device.
'SynthesisToolSpeedValue' — Synthesis tool speed value
'' (default) | character vector
Specify the synthesis tool speed value for the target device as a character vector. For more information, see the Speed section in Tool and Device.
'TargetFrequency' — Target frequency in MHz
'' (default) | character vector
Specify the target frequency in MHz as a character vector. For more information, see Target Frequency.
'MulticyclePathInfo' — Multicycle path constraint file generation
'off' (default) | 'on'
Specify whether to generate a multicycle path constraints text file. For more information, see Multicycle Path Constraints.
'MulticyclePathConstraints' — Enable-based multicycle path constraint file generation
'off' (default) | 'on'
Specify whether to generate an enable-based multicycle path constraints file. For more information, see Enable-based constraints in Multicycle Path Constraints.
Port Names and Types
'ClockEnableInputPort' — Clock enable input port name
'clk_enable' (default) | character vector
Specify the clock enable input port name as a character vector. For more information, see Clock Enable Settings.
'ClockEnableOutputPort' — Clock enable output port name
'ce_out' (default) | character vector
Clock enable output port name, specified as a character vector.
For more information, see Clock Enable output port.
'ClockInputPort' — Clock input port name
'clk' (default) | character vector
Specify the clock input port name as a character vector. For more information, see Clock Settings and Timing Controller Postfix.
'InputType' — HDL data type for input ports
'wire' or
'std_logic_vector' (default) | 'signed/unsigned'
VHDL inputs can have 'std_logic_vector' or
'signed/unsigned' data type. Verilog inputs must be 'wire'.
For more information, see Input data type in Input and Output Port Data Types.
'OutputType' — HDL data type for output ports
'Same as input data type' (default) | 'std_logic_vector' | 'signed/unsigned' | 'wire'
VHDL output can be 'Same as input data
type', 'std_logic_vector' or
'signed/unsigned'. Verilog output must be 'wire'.
For more information, see Output data type in Input and Output Port Data Types.
'ResetInputPort' — Reset input port name
'reset' (default) | character vector
Reset input port name, specified as a character vector.
For more information, see the Reset input port section in Reset Settings.
File and Variable Names
'VerilogFileExtension' — Verilog file extension
'.v' (default) | character vector
Specify the file name extension for generated Verilog files. For more information, see Language-Specific Identifiers.
'VHDLFileExtension' — VHDL file extension
'.vhd' (default) | character vector
Specify the file name extension for generated VHDL files. For more information, see the VHDLFileExtension section in Language-Specific Identifiers.
'VHDLArchitectureName' — VHDL architecture name
'rtl' (default) | character vector
For more information, see VHDL architecture name in VHDL Architecture and Library Name.
'VHDLLibraryName' — VHDL library name
'work' (default) | character vector
For more information, see VHDL library name in VHDL Architecture and Library Name.
'SplitEntityFilePostfix' — Postfix for VHDL entity file names
'_entity' (default) | character vector
For more information, see Split entity file postfix in Split entity and architecture.
'SplitArchFilePostfix' — Postfix for VHDL architecture file names
'_arch' (default) | character vector
For more information, see Split arch file postfix in Split entity and architecture.
'PackagePostfix' — Postfix for package file name
'_pkg' (default) | character vector
Specify the postfix for the package file name as a character vector. For more information, see the Package Postfix section in Language-Specific Identifiers.
'HDLMapFilePostfix' — Postfix for mapping file
'_map.txt' (default) | character vector
For more information, see Map file postfix.
'BlockGenerateLabel' — Block label postfix for VHDL GENERATE statements
'_gen' (default) | character vector
For more information, see Block generate label in Generate Statement Labels.
'ClockProcessPostfix' — Postfix for clock process names
'_process' (default) | character vector
Specify the postfix for clocked process names as a character vector. For more information, see the Clocked process postfix section in Clock Settings and Timing Controller Postfix.
'ComplexImagPostfix' — Postfix for imaginary part of complex signal
'_im' (default) | character vector
For more information, see Complex imaginary part postfix in Complex Signals Postfix.
'ComplexRealPostfix' — Postfix for imaginary part of complex signal names
'_re' (default) | character vector
For more information, see Complex real part postfix in Complex Signals Postfix.
'EntityConflictPostfix' — Postfix for duplicate VHDL entity or Verilog module names
'_block' (default) | character vector
Specify the postfix as a character vector that resolves duplicate entity or module names. For more information, see the Entity conflict postfix section in Language-Specific Identifiers.
'InstanceGenerateLabel' — Instance section label postfix for VHDL GENERATE statements
'_gen' (default) | character vector
For more information, see Instance generate label in Generate Statement Labels.
'InstancePostfix' — Postfix for generated component instance names
'' (default) | character vector
For more information, see Instance postfix in Vector and Component Instances Labels.
'InstancePrefix' — Prefix for generated component instance names
'u_' (default) | character vector
For more information, see Instance prefix in Vector and Component Instances Labels..
'OutputGenerateLabel' — Output assignment label postfix for VHDL GENERATE statements
'outputgen' (default) | character vector
For more information, see Output generate label in Generate Statement Labels.
'PipelinePostfix' — Postfix for input and output pipeline register names
'_pipe' (default) | character vector
For more information, see Pipeline postfix.
'ReservedWordPostfix' — Postfix for names conflicting with VHDL or Verilog reserved words
'_rsvd' (default) | character vector
For more information, see Reserved word postfix in Language-Specific Identifiers.
'TimingControllerPostfix' — Postfix for timing controller name
'_tc' (default) | character vector
For more information, see Timing controller postfix in Clock Settings and Timing Controller Postfix.
'VectorPrefix' — Prefix for vector names
'vector_of_' (default) | character vector
For more information, see Vector prefix in Vector and Component Instances Labels.
'EnablePrefix' — Prefix for internal enable signals
'enb' (default) | character vector
Prefix for internal clock enable and control flow enable signals, specified as a character vector. For more information, see Clock Enable Settings.
'ModulePrefix' — Prefix for modules or entity names
'' (default) | character vector
Specify a prefix for every module or entity name in the generated HDL code. HDL Coder also applies this prefix to generated script file names
For more information, see ModulePrefix in Language-Specific Identifiers.
Introduced in R2006b
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