Specify hold time for input signals and forced reset input signals
ns
Default: 2
Specify the number of nanoseconds during which the model's data input signals and forced reset input signals are held past the clock rising edge.
The hold time is expressed as a positive integer.
This option applies to reset input signals only if forced resets are enabled.
The hold time is the amount of time that reset input signals and input data are held past the clock rising edge. The following figures show the application of a hold time (thold) for reset and data input signals when the signals are forced to active high and active low.
Hold Time for Reset Input Signals
Hold Time for Data Input Signals
A reset signal is always asserted for two cycles plus thold.
To set this property, use hdlset_param
or makehdl
. To view the property value, use hdlget_param
.