Specify how long subrate signal values are held in valid state
'on' (default)
Data values for subrate signals are held in a valid state across N base-rate clock cycles, where N is the number of base-rate clock cycles that elapse per subrate sample period and N >= 2.
'off'
Data values for subrate signals are held in a valid state for only one base-rate clock
cycle. For the subsequent base-rate cycles, data is in an unknown state (expressed as
'X') until leading edge of the next subrate sample period.
In most cases, the default ('on') is the best setting for this
property. This setting matches the behavior of a Simulink® simulation,
in which subrate signals are held valid through each base-rate clock period.
In some cases (for example modeling memory or memory interfaces), it is desirable to
set HoldInputDataBetweenSamples to 'off'. In this
way, you can obtain diagnostic information about when data is in an invalid
('X') state.
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.