Speed Optimization

Critical path estimation and reduction, pipeline register insertion, loop unrolling, automated iterative clock frequency optimization

Functions

`hdlcoder.optimizeDesign`	Automatic iterative HDL design optimization
`hdlcoder.supportedDevices`	Show supported target hardware and device details

Classes

hdlcoder.OptimizationConfig hdlcoder.optimizeDesign configuration object

Blocks

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HDL Operations

Deserializer1D	Convert scalar stream or smaller vectors to vector signal
Multiply-Accumulate	Perform a multiply-accumulate operation on the inputs
Multiply-Add	Multiply-add combined operation
Serializer1D	Convert vector signal to scalar or smaller vectors

Simulink Configuration Parameters

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Optimization Overview

Topics

Adaptive Pipelining

Automatic pipeline insertion based on the target device, target frequency, and multiplier word-lengths.

Clock-Rate Pipelining

Pipeline registers insertion at the faster clock rate instead of the slower data rate.

Distributed Pipelining

Definition, benefits, and costs of distributed pipelining

Hierarchical Distributed Pipelining

Hierarchical distributed pipelining extends the scope of distributed pipelining by moving delays across hierarchical boundaries within a subsystem while preserving subsystem hierarchy.

Constrained Output Pipelining

Constrained output pipelining definition and use case.

Automatic Iterative Optimization

How automatic iterative optimization works, prerequisites and restrictions.

Critical Path Estimation Without Running Synthesis

Find the estimated critical paths in your design without using third-party synthesis tools.

Distributed Pipeline Insertion for MATLAB Function Blocks

How to optimize HDL code for MATLAB Function blocks for speed by distributing design delays and generated pipeline stages.

HDL Optimizations Across MATLAB Function Block Boundary Using MATLAB Datapath Architecture

Apply optimizations inside and across MATLAB Function blocks with other Simulink^® blocks.

Related Information

HDL Coder Clock Rate Pipelining Part 1: Introduction

HDL Coder Clock Rate Pipelining Part 2: Optimization

Featured Examples

Distributed Pipelining: Speed Optimization

Use distributed pipelining to optimize a design for speed in HDL Coder.

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Clock Rate Pipelining

Apply clock rate pipelining to optimize slow paths in your design and thereby reduce latency, increase clock frequency and decrease area usage. For more information on how to use clock-rate pipelining, see Clock-Rate Pipelining.

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Documentation