Optimization Basics

Hierarchy flattening, delay balancing, validation model, constrained overclocking, feedback loop highlighting

Model Checks

Check delay balancing setting

Simulink Configuration Parameters

Examples and How To

Speed and Area Optimizations in HDL Coder

Learn about various speed and area optimizations and how to optimize your design.

Find Feedback Loops

Highlight feedback loops that are inhibiting optimizations.

Hierarchy Flattening

Flatten subsystem hierarchy to enable more extensive area and speed optimization.

Optimization with Constrained Overclocking

Optimization with constrained overclocking and how it works.

Delay Balancing

Insert matching delays along all data paths.

Remove Redundant Logic and Unused Blocks in Generated HDL Code

Improve readability of generated HDL code and optimize area usage.

Optimize Unconnected Ports in Generated HDL Code for Simulink Models

Optimize unused ports in generated HDL code in combination with redundant logic deletion.

Simplify Constant Operations and Reduce Design Complexity in HDL Coder™

Area and timing optimizations that simplify constants and optimize mathematical operations.

Meet Timing Requirements Using Enable-Based Multicycle Path Constraints

Generate enable-based constraints for synthesis tools to meet timing requirements of multicycle paths in single clock mode.

Concepts

Generated Model and Validation Model

The generated model is an intermediate model that shows the HDL implementation architecture and includes latency.

Troubleshooting

Resolve Numerical Mismatch with Delay Balancing

Learn how to resolve numerical mismatch issues after HDL code generation.

Featured Examples

Delay Balancing and Validation Model Workflow In HDL Coder™

Delay Balancing and Validation Model Workflow In HDL Coder™

How HDL Coder can automatically balance delays within a model. HDL Coder may introduce additional delays in the HDL implementation for a given model. These delays may be introduced by either certain block implementations or by optimizations for the purpose of improving the efficiency of the hardware implementations. However, introducing delays on only certain paths can result functional behavior that is different from the original intent of the user model, thereby violating functional equivalence between the original user model and the HDL implementation.

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Control the Scope of Delay Balancing

Control the Scope of Delay Balancing

Balance delays in specific parts of a design, without balancing delays on the entire design.

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Use Multicycle Path Constraints to Meet Timing for Slow Paths

Use Multicycle Path Constraints to Meet Timing for Slow Paths

Apply multicycle path constraints in your design to meet timing requirements. Using multicycle path constraints can save area and reduce synthesis run times. For more information, see the enable-based multicycle path constraints documentation.

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Delay Balancing on multi-rate designs

Delay Balancing on multi-rate designs

How an indiscrete usage of Simulate rates on a multi- rate design can generate an undesirable HDL code, and provides few recommendations for optimal code generation.

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HDL Coder Documentation

Support