Delay Balancing and General Optimization Parameters

This page describes configuration parameters that reside in the HDL Code Generation > Target > General tab of the Configuration Parameters dialog box. Using the parameters in this section, you can use delay balancing to match delays introduced by optimizations, and partition multipliers based on a threshold value.

Balance delays

When you enable certain optimizations such as pipelining or resource sharing, or specify certain block implementations and generate code, HDL Coder™ introduces pipeline delays along certain signal paths in your model. By default, the Balance delays setting is enabled. The code generator detects these pipeline delays introduced along one path and then inserts matching delays on other paths.

To make sure that the generated model after HDL code generation is functionally equivalent to the original Simulink^® model, leave this setting enabled. If you disable this setting, HDL Coder generates a warning that numerical differences can occur in the validation model. To fix this warning, enable Balance delays on the model or run the model check Check delay balancing setting.

Settings

Default: On

On: Enables delay balancing on your model. If HDL Coder detects introduction of new delays along one path, matching delays are inserted on the other paths. When delay balancing is enabled, the generated model is functionally equivalent to the original model.
Off: The latency along signal paths might not be balanced, and the generated model might not be functionally equivalent to the original model.

Command-Line Information

Property: BalanceDelays

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can enable the BalanceDelays setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'BalanceDelays','on')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','BalanceDelays','on')
makehdl('sfir_fixed/symmetric_fir')
```

Transform non zero initial value delay

Settings

Default: On

On

Transform Delay blocks with nonzero Initial condition in your Simulink model to Delay blocks with zero Initial condition and some additional logic in the generated HDL code.

By using this transformation, HDL Coder can perform optimizations such as sharing, distributed pipelining, and clock-rate pipelining more effectively, and prevent an assertion from being triggered in the validation model.

Off

Do not transform Delay blocks with nonzero Initial condition in your Simulink model.

Command-Line Information

Property: TransformNonZeroInitValDelay

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can set the TransformNonZeroInitValDelay property to on when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'TransformNonZeroInitValDelay','on')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','TransformNonZeroInitValDelay','on')
makehdl('sfir_fixed/symmetric_fir')
```

Multiplier partitioning threshold

Settings

Default: Inf

N, where N is an integer greater than or equal to 2

Partition multipliers so that N is the maximum multiplier input bit width.

This parameter specifies the maximum input bit width for a multiplier. If at least one of the inputs to the multiplier has a bit width greater than the threshold value, the code generator splits the multiplier into smaller multipliers.

To improve hardware mapping results, set the multiplier partitioning threshold to the input bit width of the DSP or multiplier hardware on your target device.

Inf

Do not partition multipliers.

Command-Line Information

Property: MultiplierPartitioningThreshold

Type: integer

Value: integer greater than or equal to 0

Default: Inf

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can set the MultiplierPartitioningThreshold to 16 when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'MultiplierPartitioningThreshold','16')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed', 'MultiplierPartitioningThreshold','16')
makehdl('sfir_fixed/symmetric_fir')
```

Remove Unused Ports

Settings

Default: On

On: Removes ports in your design that are unused from the generated HDL code. This optimization preserves unused ports at the top-level DUT subsystem. All other unused ports are removed from the HDL code.
Off: Do not remove unused ports from the HDL code.

Command-Line Information

Property: DeleteUnusedPorts

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can set the DeleteUnusedPorts property to off when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'DeleteUnusedPorts','off')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','DeleteUnusedPorts','on')
makehdl('sfir_fixed/symmetric_fir')
```

Documentation