PN Sequence Generator

Generate pseudonoise sequence

Library:
Communications Toolbox / Comm Sources / Sequence Generators
Communications Toolbox HDL Support / Comm Sources

Description

The PN Sequence Generator block generates a sequence of pseudorandom binary numbers using a linear-feedback shift register (LFSR). Pseudonoise sequences are typically used for pseudorandom scrambling, and in direct-sequence spread-spectrum systems. For more information, see More About.

These icons shows the block with all ports enabled.

Ports

Input

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`Mask` — Output mask
binary vector

Output mask to delay the PN sequence from initial time, specified as a binary vector with N elements. N is the degree of the generator polynomial.

Dependencies

To enable this port, set Output mask source to Input port.

Data Types: double | uint8 | ufix1

`oSiz` — Output size
integer

Output size for variable-size output signals, specified as an integer. For information about variable-size signals, see Variable-Size Signal Basics (Simulink).

Dependencies

To enable this port, select Output variable-size signals and set Maximum output size source to Dialog parameter.

Data Types: double

`Ref` — Reference input
column vector

Reference input, specified as a column vector that determines the maximum and current output sequence length. The Ref input must be a variable-size signal. For information about variable-size signals, see Variable-Size Signal Basics (Simulink).

Dependencies

To enable this port, select Output variable-size signals and set Maximum output size source to Inherit from reference input.

Data Types: double

`Rst` — Reset sequence generator
0 | 1

Reset sequence generator, specified as 0 or 1. For more information, see Reset Behavior.

Dependencies

To enable this port, select Reset on nonzero input.

Data Types: Boolean

Output

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`Out` — Pseudorandom noise sequence
binary vector

PN sequence, returned as a binary vector.

Parameters

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`Generator polynomial` — Generator polynomial
`'z^6 + z + 1'` (default) | polynomial character vector | binary row vector

Generator polynomial, specified as one of the following:

A polynomial character vector that includes the number 1.
A binary row vector that represents the coefficients of the generator polynomial in order of descending power. The first and last entries must be 1. The length of this vector is (N+1), where N is the degree of the generator polynomial.
A vector containing the exponents of z for the nonzero terms of the polynomial in descending order of powers. The last entry must be 0.

For more information, see Character Representation of Polynomials.

Example: 'z^8 + z^2 + 1', [1 0 0 0 0 0 1 0 1], and [8 2 0] represent the same polynomial, p(z) = z ⁸ + z ² + 1.

Data Types: double | char

`Initial states` — Initial shift register states
`[0 0 0 0 0 1]` (default) | binary row vector

Initial shift register states, specified as a binary row vector of length N, where N is the degree of the generator polynomial.

Note

For the block to generate a nonzero sequence, the Initial states vector must contain at least one nonzero element.

Data Types: double

`Output mask source` — Output mask source
`Dialog parameter` (default) | `Input port`

Output mask source that indicates how the output mask information is given to the block, specified as:

Dialog parameter to use the Output mask vector (or scalar shift value) parameter setting.
Input port to add and use the Mask input port.

`Output mask vector (or scalar shift value)` — Output mask vector or scalar shift value
0 (default) | integer scalar | binary vector

Output mask vector or scalar shift value, specified as an integer scalar or binary row vector of length N, where N is the degree of the generator polynomial. This parameter determines the delay of the PN sequence from the initial time. For more information, see Shifting PN Sequence Starting Point.

Dependencies

To enable this parameter, set Output mask source to Dialog parameter.

Data Types: double

`Output variable-size signals` — Output variable-size signals
off (default) | on

Select this parameter to permit variable length output sequences during simulation. When set to off, fixed-length sequences are output. When set to on, variable-length sequences can be output. For information about variable-size signals, see Variable-Size Signal Basics (Simulink).

`Maximum output size source` — Maximum output size source
`Dialog parameter` (default) | `Inherit from reference port`

Maximum output size source, which indicates how the maximum sequence output size is specified.

Dialog parameter configures the block to use the Maximum output size parameter setting as the maximum permitted output sequence length. When you make this selection, the oSiz input port specifies the current size of the output signal and the block output inherits sample time from the input signal. The input value of oSiz must be less than or equal to the Maximum output size parameter.
Inherit from reference port adds the Ref input port and configures the block to inherit the sample time, maximum size, and the current output size from the variable-sized signal at the Ref input port to set the maximum permitted output sequence length.

Dependencies

To enable this parameter, select Output variable-size signals.

`Maximum output size` — Maximum output size
`[10 1]` (default) | two-element row vector

Maximum output size, specified as a two-element row vector that denotes the maximum output size for the block. The second element of the vector must be 1.

Example: [10 1] gives a 10-by-1 maximum sized output signal.

Dependencies

To enable this parameter select Output variable-size signals and set Maximum output size source to Dialog parameter.

Data Types: double

`Sample time` — Output sample time
`1` (default) | -1 | positive scalar

Output sample time, specified as -1 or a positive scalar that represents the time between each sample of the output signal. If Sample time is set to -1, the sample time is inherited from downstream. For information on the relationship between Sample time and Samples per frame, see Sample Timing.

Example: 1 specifies a sample time of 1 second.

Dependencies

To enable this parameter, clear Output variable-size signals.

Data Types: double

`Samples per frame` — Samples per frame
`1` (default) | positive integer

Samples per frame in one channel of the output signal, specified as a positive integer. For information on the relationship between Sample time and Samples per frame, see Sample Timing.

Dependencies

To enable this parameter, clear Output variable-size signals.

Data Types: double

`Reset on nonzero input` — Reset on nonzero input
off (default) | on

Select this parameter to add the Rst input port. For more information, see Reset Behavior.

`Enable bit-packed outputs` — Enable bit-packed outputs
off (default) | on

Select this parameter to make the Number of packed bits and Interpret bit-packed values as signed parameters available.

When this parameter is selected, the object outputs a column vector of length M, which contains most-significant-bit (MSB) first integer representations of bit words of length P. M is the number of samples per frame specified in the Samples per frame parameter. P is the size of the bit-packed words specified in the Number of packed bits parameter.

Note

The first bit from the left in the bit-packed word contains the most significant bit for the integer representation.

`Number of packed bits` — Number of packed bits
8 (default) | integer in the range [1, 32]

Number of packed bits, specified as an integer in the range [1, 32].

Dependencies

To enable this parameter, select Enable bit-packed outputs.

Data Types: double

`Interpret bit-packed values as signed` — Interpret bit-packed values as signed
off (default) | on

Interpret bit-packed values as signed integer data values when selected or unsigned integer data values when cleared. When selected, a 1 in the most significant bit (sign bit) indicates a negative value.

Dependencies

To enable this parameter, select Enable bit-packed outputs.

`Output data type` — Output data type
`double` (default) | `boolean` | `Smallest unsigned integer`

Output data type, specified as double, boolean, or Smallest unsigned integer.

When Enable bit-packed outputs is cleared, the output data type can be specified as a double, boolean, or Smallest unsigned integer. When the Output data type parameter is set to Smallest unsigned integer, the output data type is selected based on the settings used in the Hardware Implementation pane of the Configuration Parameters dialog box of the model. If ASIC/FPGA is selected in the Hardware Implementation pane, the output data type ufix(1) = ideal minimum one-bit size. For all other selections, it is an unsigned integer with the smallest available word length large enough to fit one bit, usually corresponding to the size of a char (for example, uint8).
When Enable bit-packed outputs is selected, the output data type can be specified as double or Smallest unsigned integer. When the Output data type parameter is set to Smallest unsigned integer, the output data type is selected based on the Interpret bit-packed values as signed and Number of packed bits parameters, and the settings used in the Hardware Implementation pane of the Configuration Parameters dialog box of the model. If ASIC/FPGA is selected in the Hardware Implementation pane, the output data type is the ideal minimum n-bit size, such as sfix(n) or ufix(n), based on the Interpret bit-packed values as signed parameter. For all other selections, it is a signed or unsigned integer with the smallest available word length large enough to fit n bits.

Model Examples

Model PN Sequence Generation With Linear Feedback Shift Register

Sequences output from the PN Sequence Generator can be modeled using a linear feedback shift register (LFSR) built with primitive Simulink® blocks.

PN Spreading for Single-User System in Multipath Channel

This model simulates pseudo-random spreading for a single-user system in a multipath transmission environment. This is similar to a mobile channel environment where the signals are received over multiple paths. Each path can have different amplitudes and delays. The receiver combines the independent paths coherently by using diversity reception to realize gains from the multipath transmissions received. The modeled system does not simulate fading effects and the receiver gets perfect knowledge of the number of paths and their respective delays.

PN Spreading for Multiuser System in Multipath Channel

This model simulates pseudo-random spreading for two users in a multipath transmission environment. This is similar to a mobile channel environment where the signals are received over multiple paths. Each path can have different amplitudes and delays. The receiver combines the independent paths coherently using diversity reception to realize gains from the multipath transmissions received. The modeled system does not simulate fading effects and the receiver gets perfect knowledge of the number of paths and their respective delays.

Block Characteristics

Data Types	`Boolean` \| `double` \| `fixed point`
Multidimensional Signals	`no`
Variable-Size Signals	`yes`

More About

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Simple Shift Register Generator

A linear-feedback shift register (LFSR), implemented as a simple shift register generator (SSRG), is used to generate PN sequences. This type of shift register is also known as a Fibonacci implementation. For an example, see Model PN Sequence Generation With Linear Feedback Shift Register.

The Generator Polynomial parameter determines the feedback connections of the shift register. It is a primitive binary polynomial in z, g_rz^r+g_r–1z^r–1+g_r–2z^r–2+...+g₀. For the coefficient, g_{k=0 to
r}, the coefficient g_k is 1 if there is a connection from the kth register to the adder. The leading term, g_r, and the constant term, g₀, of the Generator Polynomial parameter must be 1 because the polynomial must be primitive. The Initial states parameter specifies the initial values of the registers. For example, the following table indicates two sets of parameter values that correspond to a generator polynomial of p(z) = z⁸ + z² + 1.

Quantity	Example 1	Example 2
Generator polynomial	`g1 = [1 0 0 0 0 0 1 0 1]`	`g2 = [8 2 0]`
Degree of generator polynomial	8, which is `length(g1)-1`	8
Initial states	`[1 0 0 0 0 0 1 0]`	`[1 0 0 0 0 0 1 0]`

At each time step, all r registers in the generator update their values according to the value of the incoming arrow to the shift register. The adders perform addition modulo 2. The output of the LFSR reflects the sum of all connections in the m mask vector.

The Output mask vector (or scalar shift value) parameter, m, determines the shift of the PN sequence starting point. For more information, see Shifting PN Sequence Starting Point.

Shifting PN Sequence Starting Point

To shift the starting point of the PN sequence, specify the Output mask vector (or scalar shift value) parameter as:

An integer representing the length of the shift.

The default Output mask vector (or scalar shift value) setting of 0 corresponds to no shift. As illustrated in the LFSR shift register diagram in Simple Shift Register Generator, there is no shift when the only connection is along the arrow labeled m₀.

This table shows the shift that occurs when you set Output mask vector (or scalar shift value) to 0 versus a positive integer d.

	T = 0	T = 1	T = 2	...	T = d	T = d+1
Shift = 0	x₀	x₁	x₂	...	x_d	x_d+1
Shift = d	x_d	x_d+1	x_d+2	...	x_2d	x_2d+1

A binary vector whose length is equal to the degree of the generator polynomial. The LFSR shift register diagram in Simple Shift Register Generator shows Output mask vector (or scalar shift value) specified as a mask vector, m. The binary vector must have N elements, where N is the degree of the generator polynomial. To calculate the mask vector, use the shift2mask function.
The binary vector corresponds to a polynomial in z, m_r–1z^r–1 + m_r–2z^r–2 + ... + m₁z + m₀, of degree at most r–1. The mask vector that correspond to a shift of d is the vector that represents m(z) = z^d modulo g(z), where g(z) is the generator polynomial.
For example, if the degree of the generator polynomial is 4, then the mask vector that corresponds to d = 2 is [0 1 0 0], which represents the polynomial m(z) = z².

Reset Behavior

To reset the generator sequence, you must first select Reset on nonzero input to add the Rst input. Suppose that the PN Sequence Generator block outputs [1 0 0 1 1 0 1 1] when there is no reset. The following table shows the effect on the PN Sequence Generator block output for the property values indicated.

Reset Signal Properties

PN Sequence Generator block

	Reset Signal Properties	PN Sequence Generator block
No reset	Sample time = `1` Samples per frame = `1` Rst = `[0 0 0 0 0 0 0 0]`	Sample time = `1` Samples per frame = `1` Out = `[1 0 0 1 1 0 1 1]`
Scalar reset signal	Sample time = `1` Samples per frame = `1` Rst = `[0 0 0 1 0 0 0 0]`	Sample time = `1` Samples per frame = `1`
Vector reset signal	Sample time = `1` Samples per frame = `8` Rst = `[0 0 0 1 0 0 0 0]`	Sample time = `1` Samples per frame = `8`

Reset Signal

Output Signal

No reset

Sample time = 1

Samples per frame = 1

Rst = [0 0 0 0 0 0 0 0]

Sample time = 1

Samples per frame = 1

Out = [1 0 0 1 1 0 1 1]

Scalar reset signal

Sample time = 1

Samples per frame = 1

Rst = [0 0 0 1 0 0 0 0]

Sample time = 1

Samples per frame = 1

Vector reset signal

Sample time = 1

Samples per frame = 8

Rst = [0 0 0 1 0 0 0 0]

Sample time = 1

Samples per frame = 8

For the no reset case, the sequence is output without being reset. For the scalar and vector reset signal cases, the reset signal [0 0 0 1 0 0 0 0] is input to the Rst port. The sequence output is reset at the fourth bit, because the fourth bit of the reset signal is a 1 and the Sample time is 1.

For variable-sized outputs, the block only supports scalar reset signal inputs.

Sequences of Maximum Length

To generate a maximum length sequence for a generator polynomial that has the degree r, set Generator polynomial to a value from the following table. The maximum sequence length is 2^r – 1.

r	Generator Polynomial	r	Generator Polynomial	r	Generator Polynomial	r	Generator Polynomial
2	`[2 1 0]`	15	`[15 14 0]`	28	`[28 25 0]`	41	`[41 3 0]`
3	`[3 2 0]`	16	`[16 15 13 4 0]`	29	`[29 27 0]`	42	`[42 23 22 1 0]`
4	`[4 3 0]`	17	`[17 14 0]`	30	`[30 29 28 7 0]`	43	`[43 6 4 3 0]`
5	`[5 3 0]`	18	`[18 11 0]`	31	`[31 28 0]`	44	`[44 6 5 2 0]`
6	`[6 5 0]`	19	`[19 18 17 14 0]`	32	`[32 31 30 10 0]`	45	`[45 4 3 1 0]`
7	`[7 6 0]`	20	`[20 17 0]`	33	`[33 20 0]`	46	`[46 21 10 1 0]`
8	`[8 6 5 4 0]`	21	`[21 19 0]`	34	`[34 15 14 1 0]`	47	[47 14 0]
9	`[9 5 0]`	22	`[22 21 0]`	35	`[35 2 0]`	48	[48 28 27 1 0]
10	`[10 7 0]`	23	`[23 18 0]`	36	`[36 11 0]`	49	[49 9 0]
11	`[11 9 0]`	24	`[24 23 22 17 0]`	37	[37 12 10 2 0]	50	[50 4 3 2 0]
12	`[12 11 8 6 0]`	25	`[25 22 0]`	38	[38 6 5 1 0]	51	[51 6 3 1 0]
13	`[13 12 10 9 0]`	26	`[26 25 24 20 0]`	39	[39 8 0]	52	[52 3 0]
14	`[14 13 8 4 0]`	27	`[27 26 25 22 0]`	40	`[40 5 4 3 0]`	53	[53 6 2 1 0]

For more information about the shift-register configurations that these polynomials represent, see Digital Communications by John Proakis.[1].

Sample Timing

The time between output updates is equal to the product of Samples per frame and Sample time. For example, if Sample time and Samples per frame equal one, the block outputs a sample every second. If Samples per frame is increased to 10, then a 10-by-1 vector is output every 10 seconds. This ensures that the equivalent output rate is not dependent on the Samples per frame parameter.

Compatibility Considerations

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Existing models automatically update this block to current version

Behavior changed in R2020a

Starting in R2020a, Simulink^® no longer allows you to use the PN Sequence Generator block version available before R2015b.

Existing models automatically update to load the PN Sequence Generator block version announced in Source blocks output frames of contiguous time samples but do not use the frame attribute in the R2015b Release Notes. For more information on block forwarding, see Forwarding Tables (Simulink).

References

[1] Proakis, John G. Digital Communications 3rd ed. New York: McGraw Hill, 1995.

[2] Lee, J. S., and L. E. Miller. CDMA Systems Engineering Handbook. Boston and London. Artech House, 1998.

[3] Golomb, S.W. Shift Register Sequences. Laguna Hills. Aegean Park Press, 1967.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Restrictions

You can select Input port as the Output mask source on the block. In this case, the Mask input signal must be a vector of data type ufix1.
If you select Reset on nonzero input, the input to the Rst port must have data type Boolean.
Outputs of type double are not supported for HDL code generation. All other output types (including bit-packed outputs) are supported.
You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).
You cannot generate HDL for this block inside a Triggered Subsystem if the Use trigger signal as clock option is selected. See Using Triggered Subsystems for HDL Code Generation (HDL Coder).

Documentation

PN Sequence Generator

Description

Ports

Input

Mask — Output mask binary vector

Dependencies

oSiz — Output size integer

Dependencies

Ref — Reference input column vector

Dependencies

Rst — Reset sequence generator 0 | 1

Dependencies

Output

Out — Pseudorandom noise sequence binary vector

Parameters

Generator polynomial — Generator polynomial 'z^6 + z + 1' (default) | polynomial character vector | binary row vector

Initial states — Initial shift register states [0 0 0 0 0 1] (default) | binary row vector

Output mask source — Output mask source Dialog parameter (default) | Input port

Output mask vector (or scalar shift value) — Output mask vector or scalar shift value 0 (default) | integer scalar | binary vector

Dependencies

Output variable-size signals — Output variable-size signals off (default) | on

Maximum output size source — Maximum output size source Dialog parameter (default) | Inherit from reference port

Dependencies

Maximum output size — Maximum output size [10 1] (default) | two-element row vector

Dependencies

Sample time — Output sample time 1 (default) | -1 | positive scalar

Dependencies

Samples per frame — Samples per frame 1 (default) | positive integer

Dependencies

Reset on nonzero input — Reset on nonzero input off (default) | on

Enable bit-packed outputs — Enable bit-packed outputs off (default) | on

Number of packed bits — Number of packed bits 8 (default) | integer in the range [1, 32]

Dependencies

Interpret bit-packed values as signed — Interpret bit-packed values as signed off (default) | on

Dependencies

Output data type — Output data type double (default) | boolean | Smallest unsigned integer

Model Examples

Model PN Sequence Generation With Linear Feedback Shift Register

PN Spreading for Single-User System in Multipath Channel

PN Spreading for Multiuser System in Multipath Channel

Block Characteristics

More About

Simple Shift Register Generator

Shifting PN Sequence Starting Point

Reset Behavior

Sequences of Maximum Length

Sample Timing

Compatibility Considerations

Existing models automatically update this block to current version

References

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Blocks

Objects

Topics

Communications Toolbox Documentation

Support

`Mask` — Output mask
binary vector

`oSiz` — Output size
integer

`Ref` — Reference input
column vector

`Rst` — Reset sequence generator
0 | 1

`Out` — Pseudorandom noise sequence
binary vector

`Generator polynomial` — Generator polynomial
`'z^6 + z + 1'` (default) | polynomial character vector | binary row vector

`Initial states` — Initial shift register states
`[0 0 0 0 0 1]` (default) | binary row vector

`Output mask source` — Output mask source
`Dialog parameter` (default) | `Input port`

`Output mask vector (or scalar shift value)` — Output mask vector or scalar shift value
0 (default) | integer scalar | binary vector

`Output variable-size signals` — Output variable-size signals
off (default) | on

`Maximum output size source` — Maximum output size source
`Dialog parameter` (default) | `Inherit from reference port`

`Maximum output size` — Maximum output size
`[10 1]` (default) | two-element row vector

`Sample time` — Output sample time
`1` (default) | -1 | positive scalar

`Samples per frame` — Samples per frame
`1` (default) | positive integer

`Reset on nonzero input` — Reset on nonzero input
off (default) | on

`Enable bit-packed outputs` — Enable bit-packed outputs
off (default) | on

`Number of packed bits` — Number of packed bits
8 (default) | integer in the range [1, 32]

`Interpret bit-packed values as signed` — Interpret bit-packed values as signed
off (default) | on

`Output data type` — Output data type
`double` (default) | `boolean` | `Smallest unsigned integer`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.