Resettable Synchronous Subsystem

Represent resettable subsystem that has synchronous reset and enable behavior

Library

HDL Coder / HDL Subsystems

Description

The Resettable Synchronous Subsystem uses the State Control block in Synchronous mode with the Resettable Subsystem block. For subsystem blocks with state, the State Control block in Synchronous mode provides efficient reset and enable simulation behavior on hardware.

The reset port in the Resettable Synchronous Subsystem block adds reset capability to blocks inside the subsystem that have state. This includes blocks that need not have an external reset port capability, such as filters, Stateflow^® Chart, and MATLAB Function blocks. For HDL code generation, the Reset trigger type of the Reset port is set to level hold by default.

Data Type Support

See Inport for information on the data types accepted by a subsystem's input ports. See Outport for information on the data types output by a subsystem's output ports.

For more information, see Data Types Supported by Simulink in the Simulink^® documentation.

Parameters

Show port labels

Display subsystem port labels on the subsystem block.

Settings

Default: FromPortIcon

none: Does not display port labels on the subsystem block.
FromPortIcon: If the corresponding port icon displays a signal name, the parameter displays the signal name on the subsystem block. Otherwise, it displays the port block name.
FromPortBlockName: Display the name of the corresponding port block on the subsystem block.
SignalName: If the signal connected to the subsystem block port is named, this parameter displays the name. Otherwise, it displays the name of the corresponding port block.

Command-Line Information

See Block-Specific Parameters for the command-line information.

Read/Write permissions

Control user access to the contents of the subsystem.

Settings

Default: ReadWrite

ReadWrite: Enables opening and modification of subsystem contents.
ReadOnly: Enables the opening but not modification of the subsystem. If the subsystem resides in a block library, you can create and open links to the subsystem, and create and modify local copies of the subsystem. You cannot change the permissions or modify the contents of the original library instance.
NoReadOrWrite: Disables the opening or modification of subsystem. If the subsystem resides in a block library, you can create links to the subsystem in a model. You cannot open, modify, change permissions, or create local copies of the subsystem.

Command-Line Information

See Block-Specific Parameters for the command-line information.

Name of error callback function

Enter the name of the function to be called if an error occurs while Simulink software is executing the subsystem.

Settings

Default: ' '

Simulink passes two arguments to the function: the subsystem handle and a character vector that specifies the error type. If no function is specified, you get a generic error message.

Command-Line Information

See Block-Specific Parameters for the command-line information.

Permit hierarchical resolution

Specify whether to resolve names of workspace variables referenced by this subsystem.

Settings

Default: All

All: Resolve all names of workspace variables used by this subsystem, including those used to specify block parameter values and Simulink data objects (for example, Simulink.Signal objects).
ExplicitOnly: Resolve the names of workspace variables used to specify block parameter values, data store memory (where no block exists), signals, and states marked by using the signal resolution icon.
None: Do not resolve workspace variable names.

Command-Line Information

See Block-Specific Parameters for the command-line information.

Treat as atomic unit

Causes Simulink to treat the subsystem as a unit when determining the execution order of block methods.

Settings

Default: Off

On: Cause Simulink to treat the subsystem as a unit when determining the execution order of block methods. For example, when it needs to compute the output of the subsystem, Simulink software invokes the output methods of all the blocks in the subsystem before invoking the output methods of other blocks at the same level as the subsystem block.
Off: Cause Simulink to treat all blocks in the subsystem as being at the same level in the model hierarchy as the subsystem when determining block method execution order. This can cause the execution of block methods in the subsystem to be interleaved with the execution of block methods outside the subsystem.

Dependencies

This parameter enables:

Minimize algebraic loop occurrences
Sample time
Function packaging (requires a Simulink Coder™ license)

Command-Line Information

See Block-Specific Parameters for the command-line information.

Treat as grouped when propagating variant conditions

Causes Simulink software to treat the subsystem as a unit when propagating variant conditions from Variant Source blocks or to Variant Sink blocks.

Settings

Default: On

On: Simulink treats the subsystem as a unit when propagating variant conditions from Variant Source blocks or to Variant Sink blocks. For example, when Simulink computes the variant condition of the subsystem, it propagates that condition to all blocks in the subsystem.
Off: Simulink treats all blocks in the subsystem as being at the same level in the model hierarchy as the subsystem itself when determining their variant condition.

Command-Line Information

See Block-Specific Parameters for the command-line information.

Function packaging

Specify the code format to be generated for an atomic (nonvirtual) subsystem.

Settings

Default: Auto

Auto

Simulink Coder chooses the optimal format based on the type and number of subsystem instances in the model.

Inline

Simulink Coder inlines the subsystem unconditionally.

Nonreusable function

Simulink Coder software explicitly generates a separate function in a separate file. Subsystems with this setting generate functions that might have arguments depending on the Function interface parameter setting. You can name the generated function and file using parameters Function name and File name (no extension). These functions are not reentrant.

Reusable function

Simulink Coder generates a function with arguments that allows reuse of subsystem code when a model includes multiple instances of the subsystem.

This option generates a function with arguments that allows subsystem code to be reused in the generated code of a model reference hierarchy. In this case, the subsystem must be in a library.

Command-Line Information

See Block-Specific Parameters for the command-line information.

Characteristics

Data Types	Double \| Single \| Boolean \| Base Integer \| Fixed-Point \| Enumerated \| Bus
Multidimensional Signals	Yes
Variable-Size Signals	Yes
HDL Code Generation	Yes

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Actual code generation support depends on block implementation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

Architecture Description

Module (default) Generate code for the subsystem and the blocks within the subsystem.

Architecture	Description
`Module` (default)	Generate code for the subsystem and the blocks within the subsystem.
`BlackBox`	Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. Therefore, you can use a subsystem in your model to generate an interface to existing, manually written HDL code. The black-box interface generation for subsystems is similar to the Model block interface generation without the clock signals.
`No HDL`	Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a “no-op” in the HDL code.

BlackBox

Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. Therefore, you can use a subsystem in your model to generate an interface to existing, manually written HDL code.

The black-box interface generation for subsystems is similar to the Model block interface generation without the clock signals.

No HDL

Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a “no-op” in the HDL code.

Black Box Interface Customization

For the BlackBox architecture, you can customize port names and set attributes of the external component interface. See Customize Black Box or HDL Cosimulation Interface.

HDL Block Properties

General
AdaptivePipelining	Automatic pipeline insertion based on the synthesis tool, target frequency, and multiplier word-lengths. The default is `inherit`. See also AdaptivePipelining.
BalanceDelays	Detects introduction of new delays along one path and inserts matching delays on the other paths. The default is `inherit`. See also BalanceDelays.
ClockRatePipelining	Insert pipeline registers at a faster clock rate instead of the slower data rate. The default is `inherit`. See also ClockRatePipelining.
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline.
DistributedPipelining	Pipeline register distribution, or register retiming. The default is `off`. See also DistributedPipelining.
DSPStyle	Synthesis attributes for multiplier mapping. The default is `none`. See also DSPStyle.
FlattenHierarchy	Remove subsystem hierarchy from generated HDL code. The default is `inherit`. See also FlattenHierarchy.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline.
SharingFactor	Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing.
StreamingFactor	Number of parallel data paths, or vectors, that are time multiplexed to transform into serial, scalar data paths. The default is 0, which implements fully parallel data paths. See also Streaming.

If this block is not the DUT, the block property settings in the Target Specification tab are ignored. In the HDL Workflow Advisor, if you use the IP Core Generation workflow, these target specification block property values are saved with the model. If you specify these target specification block property values using hdlset_param, when you open HDL Workflow Advisor, the fields are populated with the corresponding values.

Target Specification
AdditionalTargetInterfaces	Additional target interfaces, specified as a character vector. To save this block property on the model, in the Set Target Interface task of the IP Core Generation workflow, corresponding to the DUT ports that you want to add more interfaces, select Add more.... You can then add more interfaces in the Add New Target Interfaces dialog box. Specify the type of interface, number of additional interfaces, and a unique name for each additional interface. Values: `''` (default) \| cell array of character vectors Example: `'{{'AXI4-Stream','InterfaceID','AXI4-Stream1'}}'`
ProcessorFPGASynchronization	Processor/FPGA synchronization mode, specified as a character vector. To save this block property on the model, specify the Processor/FPGA Synchronization in the Set Target Interface task of the IP Core Generation workflow. Values: `Free running` (default) \| `Coprocessing - blocking` Example: `'Free running'`
TestPointMapping	To save this block property on the model, specify the mapping of test point ports to target platform interfaces in the Set Target Interface task of the IP Core Generation workflow. Values: `''` (default) \| cell array of character vectors Example: `'{{'TestPoint','AXI4-Lite','x"108"'}}'`
TunableParameterMapping	To save this block property on the model, specify the mapping of tunable parameter ports to target platform interfaces in the Set Target Interface task of the IP Core Generation workflow. Values: `''` (default) \| cell array of character vectors Example: `'{{'myParam','AXI4-Lite','x"108"'}}'`
AXI4RegisterReadback	To save this block property on the model, specify whether you want to enable readback on AXI4 slave write registers in the Generate RTL Code and IP Core task of the IP Core Generation workflow. To learn more, see Model Design for AXI4 Slave Interface Generation. Values: `'off'` (default) \| `'on'`
AXI4SlaveIDWidth	To save this block property on the model, specify the number of AXI Master interfaces that you want to connect the DUT IP core to by using the AXI4 Slave ID Width setting in the Generate RTL Code and IP Core task of the IP Core Generation workflow. To learn more, see Define Multiple AXI Master Interfaces in Reference Designs to access DUT AXI4 Slave Interface. Values: `'off'` (default) \| `'on'`
AXI4SlavePortToPipelineRegisterRatio	To save this block property on the model, specify the number of AXI4 slave ports for which you want a pipeline register to be inserted by using the AXI4 Slave port to pipeline register ratio setting in the Generate RTL Code and IP Core task of the IP Core Generation workflow. To learn more, see Model Design for AXI4 Slave Interface Generation. Values: `'off'` (default) \| `'on'`
GenerateDefaultAXI4Slave	To save this block property on the model, specify whether you want to disable generation of default AXI4 slave interfaces in the Generate RTL Code and IP Core task of the IP Core Generation workflow. Values: `'on'` (default) \| `'off'`
IPCoreAdditionalFiles	Verilog^® or VHDL^® files for black boxes in your design. Specify the full path to each file, and separate file names with a semicolon (;). You can set this property in the HDL Workflow Advisor, in the Additional source files field. Values: `''` (default) \| character vector Example: `'C:\myprojfiles\led_blinking_file1.vhd;C:\myprojfiles\led_blinking_file2.vhd;'`
IPCoreName	IP core name, specified as a character vector. You can set this property in the HDL Workflow Advisor, in the IP core name field. If this property is set to the default value, the HDL Workflow Advisor constructs the IP core name based on the name of the DUT. Values: `''` (default) \| character vector Example: `'my_model_name'`
IPCoreVersion	IP core version number, specified as a character vector. You can set this property in the HDL Workflow Advisor, in the IP core version field. If this property is set to the default value, the HDL Workflow Advisor sets the IP core version. Values: `''` (default) \| character vector Example: `'1.3'`
IPDataCaptureBufferSize	FPGA Data Capture buffer size, specified as a character vector. Use FPGA Data Capture to observe signals in a design when running on an FPGA. The buffer size uses values that are 1282^n, where n is an integer. By default, the buffer size is 128 (n=0). The maximum value of n is 13, which means that the maximum value for buffer size is 1048576 (=1282^13). Values: `''` (default) \| character vector Example: `'1.3'`

Restrictions

You cannot use the State Control block in Classic mode or remove the State Control block from the Resettable Synchronous Subsystem block.
The Reset trigger type of the Reset port inside the subsystem must be set to level hold.
A Delay block with nonvirtual bus input signals inside a Resettable Synchronous Subsystem is not supported if you enable optimizations on the subsystem.
HDL Coder does not support these blocks inside a Resettable Synchronous Subsystem:
- All RAM blocks or blocks that infer a RAM in the generated HDL code. The RAM blocks include:
  - Single Port RAM
  - Simple Dual Port RAM
  - Dual Port RAM
  - Dual Rate Dual Port RAM
  - HDL FIFO
  - hdl.RAM system object
DSP System Toolbox
- Biquad Filter
- NCO HDL Optimized
Communications Toolbox
- Convolutional Encoder
- Viterbi Decoder
- PN Sequence Generator
- Integer-Output RS Decoder HDL Optimized
Vision HDL Toolbox
- Demosaic Interpolator
- Edge Detector
- Histogram
- Image Filter, Median Filter, Bilateral Filter
- Line Memory
- Binary and Grayscale Morphology blocks
- Pixel Stream FIFO
Wireless HDL Toolbox
- LTE Turbo Decoder and LTE Turbo Encoder
- LTE Convolutional Encoder
- LTE OFDM Demodulator and LTE OFDM Modulator
- NR Polar Encoder and NR Polar Decoder
- Viterbi Decoder
- FFT 1536
- RS Decoder
- OFDM Channel Estimator
- NR LDPC Encoder and NR LDPC Decoder

Documentation

Resettable Synchronous Subsystem

Library

Description

Data Type Support

Parameters

Show port labels

Read/Write permissions

Name of error callback function

Permit hierarchical resolution

Treat as atomic unit

Treat as grouped when propagating variant conditions

Function packaging

Characteristics

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Topics

HDL Coder Documentation

Support

Documentation

Resettable Synchronous Subsystem

Library

Description

Data Type Support

Parameters

Show port labels

Read/Write permissions

Name of error callback function

Permit hierarchical resolution

Treat as atomic unit

Treat as grouped when propagating variant conditions

Function packaging

Characteristics

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Topics

HDL Coder Documentation

Support

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.