Simulink Real-Time FPGA I/O Modules

Generate and deploy HDL code on Simulink® Real-Time™ FPGA I/O Modules (requires Simulink Real-Time)

You can generate an FPGA programming file and Simulink Real-Time FPGA I/O interface for deployment on a Speedgoat board. See IP Core Generation Workflow for Speedgoat Simulink-Programmable I/O Modules.

Classes

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hdlcoder.BoardBoard registration object that describes SoC custom board
hdlcoder.WorkflowConfigConfigure HDL code generation and deployment workflows
hdlcoder.ReferenceDesignReference design registration object that describes SoC reference design

Functions

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socExportReferenceDesignExport custom reference design for HDL Workflow Advisor
addExternalIOInterfaceDefine external IO interface for board object
addExternalPortInterfaceDefine external port interface for board object
addInternalIOInterfaceAdd and define internal IO interface between generated IP core and existing IP cores
addAXI4MasterInterfaceAdd and define AXI4 Master interface
addAXI4SlaveInterfaceAdd and define AXI4 slave interface
addAXI4StreamInterfaceAdd AXI4-Stream interface
addAXI4StreamVideoInterfaceAdd AXI4-Stream Video interface
addClockInterfaceAdd clock and reset interface
addCustomEDKDesignSpecify Xilinx EDK MHS project file
addCustomQsysDesignSpecify Altera Qsys project file
addCustomVivadoDesignSpecify Xilinx Vivado exported block design Tcl file
addIPRepositoryInclude IP modules from your IP repository folder in your custom reference design
addParameterAdd and define custom parameters for your reference design
validateReferenceDesignCheck property values in reference design object
validateBoardCheck property values in board object

Topics

IP Core Generation Workflow for Speedgoat Simulink-Programmable I/O Modules

Use the IP Core Generation workflow with Speedgoat I/O modules and embed the IP core into the reference design.

Program Target FPGA Boards or SoC Devices

How to program the target Intel or Xilinx Hardware.

Generate Simulink Real-Time Interface Subsystem for Simscape Two-Level Converter Model

Generate HDL code and Simulink Real-Time interface model from Simscape™ models.

Speedgoat FPGA Support with HDL Workflow Advisor

Implementing Simulink algorithms on FPGAs on board Speedgoat FPGA I/O modules.

Related Information

Troubleshooting

Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.

Featured Examples

FPGA Programming and Configuration on Speedgoat Simulink-Programmable I/O Modules

FPGA Programming and Configuration on Speedgoat Simulink-Programmable I/O Modules

Select and run HDL code generation and synthesis workflow for a Speedgoat target device.

Open Script
Deploy Simscape Buck Converter Model to Speedgoat IO Module Using HDL Workflow Script

Deploy Simscape Buck Converter Model to Speedgoat IO Module Using HDL Workflow Script

Deploy buck converter modeled in Simscape to Speedgoat IO modules using HDL Workflow script.

Open Script
Hardware-in-the-Loop Implementation of Simscape Model on Speedgoat FPGA I/O Modules

Hardware-in-the-Loop Implementation of Simscape Model on Speedgoat FPGA I/O Modules

Synthesize and generate FPGA bitstream from a Simscape™ half-wave rectifier model and download the bitstream to a Speedgoat FPGA I/O 334-325K target for Hardware-in-the-Loop (HIL) implementation.

Open Script

HDL Coder Documentation

Support