Class: hdlcoder.ReferenceDesign
Package: hdlcoder
Specify Xilinx Vivado exported block design Tcl file
addCustomVivadoDesign('CustomBlockDesignTcl',bd_tcl_file)
addCustomVivadoDesign('CustomBlockDesignTcl', specifies
the exported block design Tcl file that contains the Xilinx® Vivado® embedded
system design. Use this method if your synthesis tool is Xilinx Vivado.bd_tcl_file)
If you have more than one AXI Master IP, in the custom block design Tcl file, you must make sure that the AXI Master IPs connect to the same AXI Interconnect IP. The AXI4 slave interfaces in the HDL IP core also connect to this Interconnect.
If your synthesis tool is Xilinx ISE, use the addCustomEDKDesign method.
If your synthesis tool is Altera® Quartus II,
use the addCustomQsysDesign method.