Class: hdlcoder.ReferenceDesign
Package: hdlcoder
Specify Altera Qsys project file
addCustomQsysDesign('CustomQsysPrjFile',qsys_project_file)
addCustomQsysDesign('CustomQsysPrjFile', specifies
the Qsys project file that contains the Altera® Qsys embedded
system design. Use this method if your synthesis tool is Altera Quartus
II.qsys_project_file)
If you have more than one AXI Master IP, in the custom qsys project file, you must make sure that the AXI Master IPs connect to the same AXI Interconnect IP. The AXI4 slave interfaces in the HDL IP core also connect to this Interconnect.
If your synthesis tool is Xilinx® Vivado®,
use the addCustomVivadoDesign method.
If your synthesis tool is Xilinx ISE, use the addCustomEDKDesign method.