Single Port RAM

Single port RAM

Library

HDL Coder / HDL RAMs

Description

The Single Port RAM block models RAM that supports sequential read and write operations.

If you want to model RAM that supports simultaneous read and write operations, use the Dual Port RAM or Simple Dual Port RAM.

Parameters

Address port width

Address bit width. Minimum bit width is 2, and maximum bit width is 29. The default is 8.

Output data during write

Controls the output data, dout, during a write access.

New data (default): During a write, new data appears at the output port, dout.
Old data: During a write, old data appears at the output port, dout.

Ports

The block has the following ports:

din

Data input. The data can have any width. It inherits the width and data type from the input signal.

Data type: scalar fixed point, integer, or complex

addr

Write address.

Data type: scalar unsigned integer (uintN) or unsigned fixed point (ufixN) with a fraction length of 0

we

Write enable.

Data type: Boolean

dout

Output data from address, addr.

Algorithms

expand all

HDL code generated for RAM blocks has:

A latency of one clock cycle for read data output.
No reset signal, because some synthesis tools do not infer a RAM from HDL code if it includes a reset.

Code generation for a RAM block creates a separate file, blockname.ext. blockname is derived from the name of the RAM block. ext is the target language file name extension.

RAM Initialization

Code generated to initialize a RAM is intended for simulation only. Synthesis tools can ignore this code.

Implement RAM With or Without Clock Enable

The HDL block property, RAMArchitecture, enables or suppresses generation of clock enable logic for all RAM blocks in a subsystem. You can set RAMArchitecture to the following values:

WithClockEnable (default): Generates RAM using HDL templates that include a clock enable signal, and an empty RAM wrapper.
WithoutClockEnable: Generates RAM without clock enables, and a RAM wrapper that implements the clock enable logic.

Some synthesis tools do not infer RAM with a clock enable. If your synthesis tool does not support RAM structures with a clock enable, and cannot map your generated HDL code to FPGA RAM resources, set RAMArchitecture to WithoutClockEnable.

To learn how to generate RAM without clock enables for your design, see the Getting Started with RAM and ROM example. To open the example, at the command prompt, enter:

hdlcoderramrom

RAM Inference Limitations

Depending on your synthesis tool and target device, the setting of Output data during write can affect RAM inference.

If you use RAM blocks to perform concurrent read and write operations, verify the read-during-write behavior in hardware. The read-during-write behavior of the RAM blocks in Simulink^® matches that of the generated behavioral HDL code. However, if a synthesis tool does not follow the same behavior during RAM inference, it causes the read-during-write behavior in hardware to differ from the behavior of the Simulink model or generated HDL code.

Your synthesis tool might not map the generated code to RAM for the following reasons:

Small RAM size: your synthesis tool uses registers to implement a small RAM for better performance.
A clock enable signal is present. You can suppress generation of a clock enable signal in RAM blocks, as described in Implement RAM With or Without Clock Enable.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline.
RAMDirective	Specify whether to map RAM blocks in your design to distributed RAMs, block RAMs, or UltraRAM memory on the target FPGA. See also RAMDirective.

Complex Data Support

This block supports code generation for complex signals.

Documentation

Single Port RAM

Library

Description

Parameters

Ports

Algorithms

RAM Initialization

Implement RAM With or Without Clock Enable

RAM Inference Limitations

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Blocks

HDL Coder Documentation

Support

Documentation

Single Port RAM

Library

Description

Parameters

Ports

Algorithms

RAM Initialization

Implement RAM With or Without Clock Enable

RAM Inference Limitations

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Blocks

HDL Coder Documentation

Support

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.