NCO HDL Optimized

Generate real or complex sinusoidal signals—optimized for HDL code generation

Library:
DSP System Toolbox HDL Support / Signal Operations
DSP System Toolbox HDL Support / Sources

Description

The NCO HDL Optimized block generates real or complex sinusoidal signals, while providing hardware-friendly control signals. The block uses the same phase accumulation and lookup table algorithm as implemented in the NCO block. The block uses quantized integer accumulation to create a sinusoid signal.

The NCO HDL Optimized block provides these features:

Optional frame-based output.
A lookup table compression option to reduce the lookup table size. This compression results in less than one LSB loss in precision. See Lookup Table Compression for more information.
An optional input port for external dither.
An optional reset port that resets the phase accumulator to its initial value.
An optional output port for the current NCO phase.

Given a sample time, T_s, and the desired output frequency resolution Δf, calculate the necessary accumulator size by using $N a c c = ceil (\log_{2} (\frac{1}{T_{s} \cdot Δ f}))$ .

Assuming that your desired output frequency F_o is much lower than the Nyquist frequency, you can determine the acceptable quantization at the output of the accumulator by using an approximation for the noise per bit in dB and the desired spurious free dynamic range (SFDR). The quantized word length to achieve a specified SFDR is $N q = ceil (\frac{S F D R - 12}{6})$ .

For a desired output frequency F_o, calculate the phase increment by using $p h a s e i n c r e m e n t = round (F_{0} T_{s} 2^{N a c c})$ , where Nacc is the accumulator word length. You can specify the phase increment using a parameter or an input port.

Given a desired phase offset (in radians), calculate the phase offset input value by using $p h a s e o f f s e t = \frac{2^{N a c c} \cdot d e s i r e d p h a s e o f f s e t}{2 π}$ . You can specify the phase offset using a parameter or an input port.

Ports

Note

This block appears in the Sources libraries with Phase increment source parameter set to Property. The only input port is valid.
This block appears in the Signal Operations libraries with Phase increment source parameter set to Input port. This configuration shows the optional input port inc.

This icon shows the optional ports of the NCO HDL Optimized block.

Input

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`inc` — Phase increment (optional)
scalar integer

Phase increment, specified as a scalar integer.

double and single data types are supported for simulation but not for HDL code generation.

Dependencies

To enable this port, set the Phase increment source parameter to Input port.

`offset` — Phase offset (optional)
scalar integer

Phase offset, specified as a scalar integer.

double and single data types are supported for simulation but not for HDL code generation.

Dependencies

To enable this port, set the Phase offset source parameter to Input port.

`dither` — Dither (optional)
integer | column vector of integers

Dither, specified as an integer or a column vector of integers. The length of the vector must equal the Samples per frame parameter value.

double and single data types are supported for simulation but not for HDL code generation.

Dependencies

To enable this port, set the Dither source parameter to Input port.

`valid` — Control signal that enables NCO operation
scalar

Control signal that enables NCO operation, specified as a Boolean scalar. When this signal is 1, the block increments the phase and captures any input values. When this signal is 0, the block holds the phase accumulator and ignores any input values.

When the Samples per frame parameter is greater than 1, this value enables processing of Samples per frame samples.

Data Types: Boolean

`reset accum` — Control signal that resets the accumulator (optional)
scalar

Control signal that resets the accumulator, specified as a Boolean scalar. When this signal is 1, the block resets the accumulator to its initial value. This signal does not reset the output samples in the pipeline.

Dependencies

To enable this port, select the Enable accumulator reset input port parameter.

Data Types: Boolean

Output

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`sin, cos, exp` — Generated waveform
scalar | column vector

Generated waveform, returned as a scalar or as a column vector with length equal to the Samples per frame parameter value. The output can be a single port that returns sin or cos values, a single port that returns exp values representing cosine + j*sine, or two ports that return sin and cos values, respectively. When all input values are fixed-point type or all input ports are disabled, the block determines the output type using the Output data type parameter. When any input value is floating-point type, the block ignores the Output data type parameter. In this case, the block returns the waveform as floating-point values.

Floating-point data types are supported for simulation but not for HDL code generation.

Dependencies

By default, this output port is a sine wave, sin. The port label and format changes based on the Type of output signal parameter.

`phase` — Current phase of NCO (optional)
scalar | column vector

Current phase of NCO, returned as a scalar or as a column vector with length equal to the Samples per frame parameter value. The phase is the output of the quantized accumulator with offset and increment applied. If quantization is disabled, this port returns the output of the accumulator with offset and increment applied.

The values are of type fixdt(1,N,0), where N is the Number of quantizer accumulator bits parameter value. If quantization is disabled, then N is the Accumulator Word length parameter value If any input value is floating-point type, the block returns the phase as a floating-point value.

Floating-point data types are supported for simulation but not for HDL code generation.

Dependencies

To enable this port, select the Enable phase port parameter.

Data Types: single | double | fixdt(1,N,0)

`valid` — Control signal that indicates validity of output data
scalar

Control signal that indicates validity of output data, returned as a Boolean scalar. When output valid is 1, the values on the sin, cos, exp, and phase ports are valid. When output valid is 0, the values on the output ports are not valid.

When the Samples per frame parameter is greater than 1, this signal indicates the validity of all elements in the output vector.

Data Types: Boolean

Parameters

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Main

Note

This block supports double and single input for simulation but not for HDL code generation. When all input values are fixed-point type or all input ports are disabled, the block determines the output type using the Output data type parameter. When any input value is floating-point type, the block ignores the Output data type parameter. In this case, the block returns the waveform and optional phase as floating-point values.

To use the Fixed-Point Designer™ data type override feature, you can obtain a double output value by applying double input data to one of the optional ports.

`Phase increment source` — Source of phase increment
`Input port` (default) | `Property`

You can set the phase increment with an input port or by entering a value for the parameter. If you select Property, the Phase increment parameter appears for you to enter a value. If you select Input port, the inc port appears on the block.

`Phase increment` — Phase increment for generated waveform
`100` (default) | integer

Phase increment for the generated the waveform, specified as an integer.

Dependencies

To enable this parameter, set the Phase increment source parameter to Property.

`Phase offset source` — Source of phase offset
`Input port` (default) | `Property`

You can set the phase offset with an input port or by entering a value for the parameter. If you select Property, the Phase offset parameter appears for you to enter a value. If you select Input port, the offset port appears on the block.

`Phase offset` — Phase offset for generated waveform
`0` (default) | integer

Phase offset for the generated waveform, specified as an integer.

Dependencies

To enable this parameter, set the Phase offset source parameter to Property.

`Dither source` — Source of number of dither bits
`Property` (default) | `Input port` | `None`

You can set the dither from an input port or from a parameter. If you select Property, the Number of dither bits parameter appears. If you select Input port, a port appears on the block. If you select None, the block does not add dither.

`Number of dither bits` — Bits used to express dither
`4` (default) | positive integer

Number of dither bits, specified as a positive integer.

Dependencies

To enable this parameter, set the Dither source parameter to Property.

`Samples per frame` — Vector size for frame-based input and output
`1` (default) | positive integer

When you set this value to 1, the block has scalar input and output. When this value is greater than 1, the dither port expects a column vector of length Samples per frame and the sin, cos, exp, and phase ports return column vectors of length Samples per frame.

`Enable look up table compression method` — Compress the lookup table
`off` (default) | `on`

By default, the block implements a noncompressed lookup table, and the output of this block matches the output of the NCO block. When you enable this option, the block implements a compressed lookup table. The Sunderland compression method reduces the size of the lookup table, losing less than one LSB of precision. The spurious free dynamic range (SFDR) is empirically 1–3 dB lower than the noncompressed case. The hardware savings of the compressed lookup table allow room to improve performance by increasing the word length of the accumulator and the number of quantize bits. For detail of the compression method, see Algorithms.

`Enable accumulator reset input port` — Enable reset control signal
`off` (default) | `on`

Select this parameter to enable the reset accum port. When reset accum is 1, the block resets the accumulator to its initial value.

`Type of output signal` — Format of output waveform
`Sine` (default) | `Cosine` | `Complex exponential` | `Sine and cosine`

If you select Sine or Cosine, the block shows the applicable port, sin or cos. If you select Complex exponential, the output is of the form cosine + j*sine and the port is labeled exp. If you select Sine and cosine, the block shows two ports, sin and cos.

`Enable phase port` — Output current phase
`off` (default) | `on`

Select this parameter to return the current NCO phase on the phase port. The phase is the output of the quantized accumulator, with offset and increment applied. If quantization is disabled, this port returns the output of the accumulator, with offset and increment applied.

Data Types

`Rounding Mode` — Rounding mode for fixed-point operations
`Floor` (default)

Rounding mode for fixed-point operations. Rounding Mode is a read-only parameter with value Floor.

`Overflow mode` — Overflow mode for fixed-point operations
`Wrap` (default)

Overflow mode for fixed-point operations. Overflow mode is a read-only parameter. Fixed-point numbers wrap around on overflow.

`Accumulator Data Type` — Accumulator data type
`Binary point scaling` (default)

Accumulator data type description. This parameter is read-only, with value Binary point scaling. The block defines the fixed-point data type using the Accumulator Signed, Accumulator Word length, and Accumulator Fraction length parameters.

`Accumulator Signed` — Signed or unsigned accumulator data format
`Signed` (default)

This parameter is read-only. All output is signed format.

`Accumulator Word length` — Accumulator word length
`16` (default) | integer

Units are in bits. This value must include the sign bit.

If you clear the Quantize phase parameter, this parameter must be less than or equal to 17 bits for HDL code generation. This limitation is because, in the nonquantized case, the lookup table of sine values has 2^{AccumulatorWordLength-2} entries.

`Accumulator Fraction length` — Accumulator fraction length
`0` (default) | integer

This parameter is read-only. The accumulator fraction length is zero bits.

The accumulator operates on integers. If the phase increment is fixdt type with a fractional part, the block returns an error.

`Quantize phase` — Quantize accumulated phase
`off` (default) | `on`

When you select this parameter, the block quantizes the result of the phase accumulator to a fixed bit-width. This quantized value is used to select a waveform value from the lookup table. Select the resolution of the lookup table by using the Number of quantizer accumulator bits parameter.

The frequency resolution of an NCO is defined by $Δ f = \frac{1}{T_{s} \cdot 2^{N}} Hz$ , where N is the Number of quantizer accumulator bits parameter value.

When you clear this parameter, the block uses the full accumulator data type as the address of the lookup table. In this case, N is the Accumulator Word length parameter value.

`Number of quantizer accumulator bits` — Number of quantizer accumulator bits
`12` (default) | integer

Number of quantizer accumulator bits, specified as an integer scalar greater than 4 and less than the accumulator word length. This parameter must be less than or equal to 17 bits for HDL code generation. The lookup table of sine values has 2^{NumQuantizerAccumBits-2} entries.

Dependencies

To enable this parameter, select the Quantize phase parameter.

`Output Data Type` — Output data type
`Binary point scaling` (default) | `double` | `single`

Specify the data type for the sin, cos, and exp ports. This parameter is ignored if any input is of floating-point type. In that case, the output data type is floating-point.

If you select Binary point scaling, the block defines the fixed-point data type using the Output Signed, Output Word length, and Output Fraction length parameters.

`Output Signed` — Signed or unsigned output data format
`Signed` (default)

This parameter is read-only. All output is signed format.

`Output Word length` — Output word length
`16` (default) | integer

Units are in bits. This value must include the sign bit.

`Output Fraction length` — Output fraction length
`14` (default) | integer

Units are in bits.

Model Examples

HDL Optimized QAM Transmitter and Receiver

Implement a 64-QAM transmitter and receiver for HDL code generation and hardware implementation.

Algorithms

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The NCO implementation depends on whether you select Enable look up table compression method.

Without lookup table compression, the block uses the same quarter-sine lookup table as the NCO block. The size of the LUT is 2^{Number of quantizer accumulator bits-2}×Output word length bits.

If you do not enable Quantize phase, then Number of quantizer accumulator bits=Accumulator Word length. Consider the impact on simulator memory and hardware resources when you select these parameters.

Lookup Table Compression

When you select lookup table (LUT) compression, the NCO HDL Optimized block applies the Sunderland compression method. Sunderland techniques use trigonometric identities to divide each phase of the quarter sine wave into three components and express it as:

$\sin (A + B + C) = \sin (A + B) \cos (C) + \cos (A) \cos (B) \sin (C) - \sin (A) \sin (B) \sin (C)$

If the quarter-sine phase has Q-2 bits, then the phase components A and B have a word length of LA=LB=ceil((Q-2)/3). Phase component C contains the remaining phase bits. If the phase has 12 bits, then the quarter sine phase has 10 bits, and the components are defined as:

A, the four most significant bits
$(0 \leq A \leq \frac{π}{2})$
B, the next four bits
$(0 \leq B \leq \frac{π}{2} \times 2^{- 4})$
C, the remaining two least significant bits
$(0 \leq C \leq \frac{π}{2} \times 2^{-}^{8})$

Given the relative sizes of A, B, and C, the equation can be approximated by:

$\sin (A + B + C) \approx \sin (A + B) + \cos A \sin C$

The NCO HDL Optimized block implements this equation with one LUT for $\sin (A + B)$ and one LUT for $\cos (A) \sin (C)$ . The second term is a fine correction factor that you can truncate to fewer bits without losing precision. Therefore, the second LUT returns a four-bit result.

With the default accumulator size of 16 bits, and the default quantized phase width of 12 bits, the LUTs use 2⁸×16 plus 2⁶×4 bits (4.5 kb). For comparison, a quarter-sine lookup table without compression uses 2¹⁰×16 bits (16 kb). The compression approximation is accurate within one LSB, resulting in an SNR of at least 60 dB on the output. See [1].

Control Signals

The block has two input control signals, reset accum (optional) and valid, and one output control signal, valid. When reset accum is 1, the block sets the phase accumulator to its initial value. When the input valid is 1, the block increments the phase and captures any input values. When this signal is 0, the block holds the phase accumulator and ignores any input values. When the output valid signal is 1, the values on the other output ports are valid.

Latency

The latency of the NCO HDL Optimized block is six cycles.

Compatibility Considerations

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HDL-optimized NCO requires valid input port

Behavior changed in R2020a

In previous releases, the input validIn port of the NCO HDL Optimized block was optional. It is now required, and renamed valid. If you are using no other input ports, the block uses the valid signal as an enable signal.

HDL-optimized NCO with floating-point inputs applies phase quantization

Behavior changed in R2020a

The output waveform returned from floating-point input values has changed. The output waveform now matches that returned from the same input values specified in fixed-point types.

Prior to R2020a, when using floating-point input types, the NCO HDL Optimized block did not quantize the phase internally. The block expected floating-point phase increment and phase offset inputs specified in radians. Now, the block quantizes the phase internally, and you must specify the input phase increment and offset in terms of the quantized size, for both floating-point and fixed-point input types.

For example, prior to R2020a, for a floating-point HDL NCO to generate output samples with a desired output frequency of F₀ and sample frequency of F_s, you had to specify the phase increment as 2π(F₀/F_s) and phase offset as π/2.

Starting in R2020a, you must specify the phase increment and phase offset in terms of the quantized size, N. These input values are the same as the input values you use with fixed-point types. Specify the phase increment as (F₀×2^N)/F_s, and the phase offset as (π/2)×2^N/2π, or 2^N/4.

NCO HDL Optimized block now ignores LUTRegisterResetType parameter

Behavior changed in R2020a

In previous releases, you could choose from two options for the LUTRegisterResetType parameter on the HDL Block Properties dialog of the NCO HDL Optimized block. The two options were default, and none. Starting in R2020a, the block ignores the parameter setting and uses none for this parameter value. This option does not connect a reset signal to the LUT registers. This configuration enables the synthesis tool to determine whether to implement the lookup tables with LUTs or BRAM.

References

[1] Cordesses, L., "Direct Digital Synthesis: A Tool for Periodic Wave Generation (Part 1)." IEEE Signal Processing Magazine. Volume 21, Issue 4, July 2004, pp. 50–54.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Restrictions

When you set Dither source to Property, the block adds random dither every cycle. If you generate a validation model with these settings, a warning is displayed. Random generation of the internal dither can cause mismatches between the models. You can increase the error margin for the validation comparison to account for the difference. You can also disable dither or set Dither source to Input port to avoid this issue.
You cannot use the NCO HDL Optimized block inside a Resettable Synchronous Subsystem (HDL Coder).

Documentation

NCO HDL Optimized

Description

Ports

Input

inc — Phase increment (optional) scalar integer

Dependencies

offset — Phase offset (optional) scalar integer

Dependencies

dither — Dither (optional) integer | column vector of integers

Dependencies

valid — Control signal that enables NCO operation scalar

reset accum — Control signal that resets the accumulator (optional) scalar

Dependencies

Output

sin, cos, exp — Generated waveform scalar | column vector

Dependencies

phase — Current phase of NCO (optional) scalar | column vector

Dependencies

valid — Control signal that indicates validity of output data scalar

Parameters

Main

Phase increment source — Source of phase increment Input port (default) | Property

Phase increment — Phase increment for generated waveform 100 (default) | integer

Dependencies

Phase offset source — Source of phase offset Input port (default) | Property

Phase offset — Phase offset for generated waveform 0 (default) | integer

Dependencies

Dither source — Source of number of dither bits Property (default) | Input port | None

Number of dither bits — Bits used to express dither 4 (default) | positive integer

Dependencies

Samples per frame — Vector size for frame-based input and output 1 (default) | positive integer

Enable look up table compression method — Compress the lookup table off (default) | on

Enable accumulator reset input port — Enable reset control signal off (default) | on

Type of output signal — Format of output waveform Sine (default) | Cosine | Complex exponential | Sine and cosine

Enable phase port — Output current phase off (default) | on

Data Types

Rounding Mode — Rounding mode for fixed-point operations Floor (default)

Overflow mode — Overflow mode for fixed-point operations Wrap (default)

Accumulator Data Type — Accumulator data type Binary point scaling (default)

Accumulator Signed — Signed or unsigned accumulator data format Signed (default)

Accumulator Word length — Accumulator word length 16 (default) | integer

Accumulator Fraction length — Accumulator fraction length 0 (default) | integer

Quantize phase — Quantize accumulated phase off (default) | on

Number of quantizer accumulator bits — Number of quantizer accumulator bits 12 (default) | integer

Dependencies

Output Data Type — Output data type Binary point scaling (default) | double | single

Output Signed — Signed or unsigned output data format Signed (default)

Output Word length — Output word length 16 (default) | integer

Output Fraction length — Output fraction length 14 (default) | integer

Model Examples

HDL Optimized QAM Transmitter and Receiver

Algorithms

Lookup Table Compression

Control Signals

Latency

Compatibility Considerations

HDL-optimized NCO requires valid input port

HDL-optimized NCO with floating-point inputs applies phase quantization

NCO HDL Optimized block now ignores LUTRegisterResetType parameter

References

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Blocks

Objects

DSP System Toolbox Documentation

Support

`inc` — Phase increment (optional)
scalar integer

`offset` — Phase offset (optional)
scalar integer

`dither` — Dither (optional)
integer | column vector of integers

`valid` — Control signal that enables NCO operation
scalar

`reset accum` — Control signal that resets the accumulator (optional)
scalar

`sin, cos, exp` — Generated waveform
scalar | column vector

`phase` — Current phase of NCO (optional)
scalar | column vector

`valid` — Control signal that indicates validity of output data
scalar

`Phase increment source` — Source of phase increment
`Input port` (default) | `Property`

`Phase increment` — Phase increment for generated waveform
`100` (default) | integer

`Phase offset source` — Source of phase offset
`Input port` (default) | `Property`

`Phase offset` — Phase offset for generated waveform
`0` (default) | integer

`Dither source` — Source of number of dither bits
`Property` (default) | `Input port` | `None`

`Number of dither bits` — Bits used to express dither
`4` (default) | positive integer

`Samples per frame` — Vector size for frame-based input and output
`1` (default) | positive integer

`Enable look up table compression method` — Compress the lookup table
`off` (default) | `on`

`Enable accumulator reset input port` — Enable reset control signal
`off` (default) | `on`

`Type of output signal` — Format of output waveform
`Sine` (default) | `Cosine` | `Complex exponential` | `Sine and cosine`

`Enable phase port` — Output current phase
`off` (default) | `on`

`Rounding Mode` — Rounding mode for fixed-point operations
`Floor` (default)

`Overflow mode` — Overflow mode for fixed-point operations
`Wrap` (default)

`Accumulator Data Type` — Accumulator data type
`Binary point scaling` (default)

`Accumulator Signed` — Signed or unsigned accumulator data format
`Signed` (default)

`Accumulator Word length` — Accumulator word length
`16` (default) | integer

`Accumulator Fraction length` — Accumulator fraction length
`0` (default) | integer

`Quantize phase` — Quantize accumulated phase
`off` (default) | `on`

`Number of quantizer accumulator bits` — Number of quantizer accumulator bits
`12` (default) | integer

`Output Data Type` — Output data type
`Binary point scaling` (default) | `double` | `single`

`Output Signed` — Signed or unsigned output data format
`Signed` (default)

`Output Word length` — Output word length
`16` (default) | integer

`Output Fraction length` — Output fraction length
`14` (default) | integer

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.