System Integration of DL Processor IP Core

Manually integrate the generated deep learning (DL) processor IP core into your system design

Deep Learning HDL Toolbox™ generates a deep learning (DL) processor IP core and builds the FPGA bitstreams for the supported FPGA boards. For more information, see Generate Custom Processor IP and Generate Custom Bitstream.

You can accelerate the integration of the generated DL processor IP core into your system design by:

Generating the DL Processor IP core.
Using the compiler generated external memory buffer allocation.
Formatting the input and output external memory data.
Creating the AXI4 register maps. The AXI4 registers allow MATLAB^® to control and program the DL processor IP core.

Topics

Get Started

Deep Learning Processor IP Core

Learn about the generated deep learning processor IP core.

Compiler Output

Determine the target-specific external memory offsets based on your network and hardware design.

External Memory Data Format

Define the input and output external memory data format.

Deep Learning Processor Register Map

Use MATLAB or other AXI4 master devices to control and program the deep learning processor IP core.

Featured Examples

Authoring a Reference Design for Live Camera Integration with Deep Learning Processor IP Core

Create an HDL Coder™ reference design that contains a generated deep learning processor IP core. The reference design receives a live camera input and uses a deployed series network to classify the objects in the camera input. This figure is a high-level architectural diagram that shows the reference design that will be implemented on the Xilinx™ Zynq™ Ultrascale+(TM) MPsoC ZCU102 Evaluation Kit.

Open Script

Run a Deep Learning Network on FPGA with Live Camera Input

Model preprocessing logic that receives a live camera input. You implement it on a Zynq® Ultrascale+(TM) MPSoC ZCU102 board by using a custom video reference design that has an integrated deep learning processor IP core for object classification. This example uses the HDL Coder™ HW/SW co-design workflow.