When you generate HDL code, you can optionally generate an HDL test bench that verifies the generated HDL DUT against test vectors saved from your Simulink model.
makehdltb | Generate HDL test bench from model or subsystem |
SimulationTool | Simulator for which the tool generates build-and-run scripts for the test bench and optional code coverage |
UseFileIOInTestBench | Specify whether to use data files for reading and writing test bench stimulus and reference data |
Learn how HDL test bench generation works.
Choose a Test Bench for Generated HDL Code
Select a generated test bench.
Verify Generated Code from Simulink Model Using HDL Test Bench
Learn how to generate a HDL test bench to verify the VHDL or Verilog Code.