Clock Input Signals
Force clock
Specify whether the test bench forces clock input signals.
Settings
Default: On
On The test bench forces the clock input signals. When this option is selected, the clock high and low time settings control the clock waveform.
OffA user-defined external source forces the clock input signals.
Dependencies
This property enables the Clock high time and Clock high time options. This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.
Command-Line Information
Property:
ForceClock |
| Type: character vector |
Value:
'on' | 'off' |
Default:
'on' |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
See Also
Clock high time (ns)
Specify the period, in nanoseconds, during which the test bench drives clock input signals high (1).
Settings
Default: 5
The Clock high time and Clock low time properties define the period and duty cycle for the clock signal. Using the defaults, the clock signal is a square wave (50% duty cycle) with a period of 10 ns.
Dependency
This parameter is enabled when Force clock is selected.
Command-Line Information
Property:
ClockHighTime |
| Type: integer |
| Value: positive integer |
| Default: 5 |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
See Also
Clock low time (ns)
Specify the period, in nanoseconds, during which the test bench drives clock input signals low (0).
Settings
Default: 5
The Clock high time and Clock low time properties define the period and duty cycle for the clock signal. Using the defaults, the clock signal is a square wave (50% duty cycle) with a period of 10 ns.
Dependency
This parameter is enabled when Force clock is selected.
Command-Line Information
Property:
ClockLowTime |
| Type: integer |
| Value: positive integer |
| Default: 5 |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.