Multi-file test bench

Divide generated test bench into helper functions, data, and HDL test bench code files.

Description

You can use this setting to specify how you want to divide files that contain the test bench code, data, and helper functions.

The file names are derived from the name of the DUT, the Test bench name postfix property, and the Test bench data file name postfix property as:

DUTname_TestBenchPostfix_TestBenchDataPostfix

For example, if the DUT name is symmetric_fir, and the target language is VHDL^®, the default test bench file names are:

symmetric_fir_tb.vhd: test bench code
symmetric_fir_tb_pkg.vhd: helper functions package
symmetric_fir_tb_data.vhd: data package

If the DUT name is symmetric_fir and the target language is Verilog^®, the default test bench file names are:

symmetric_fir_tb.v: test bench code
symmetric_fir_tb_pkg.v: helper functions package
symmetric_fir_tb_data.v: test bench data

Settings

Default: Off

On: Write three separate HDL files. There is a separate file for test bench code, helper functions, and test bench data.
Off: Write two separate HDL files. One file contains the HDL test bench code. The other file contains the helper functions package and test bench data.

Dependency

When this property is selected, Test bench data file name postfix is enabled.

This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.

Command-Line Information

Property: MultifileTestBench

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

Documentation