The Ready Generator subsystem controls input data samples based on the FFT Length, CP Length, number of left and right guard carriers, and DC null insertion status.

When you set the OFDM parameters source parameter to Property, these equations apply.

When you set the OFDM parameters source parameter to Port, these equations apply.

This figure shows the ready signal generation for a default block configuration.

The block stores input valid active subcarrier data, reads it, and forms a symbol of FFT length by placing the data at the center, and guard subcarriers at the edges of the symbol based on the number of left and right guard subcarrier values provided.

This block repeats FFT-length number of samples until it forms the maximum FFT length. For this operation, the block buffers the input samples first and then repeats the samples based on the maximum FFT length value. This repetition mechanism helps to avoid scaling at the FFT block input. This block is optional and available only when you set the OFDM parameters source parameter to Input port. When you set the OFDM parameters source parameter to Property, the FFT length value provided in the block mask is set as the maximum FFT length. The block does not need to repeat the samples in this context.

For example, if the FFT length is 128 and the maximum FFT length is 2048, each OFDM symbol consists of 128 samples. The block converts these 128 samples to 2048 samples by repeating the 128 samples 16 times. After the block generates 2048 data samples, it sends data and valid input signals to the next block.

The IFFT block converts a frequency-domain signal to a time-domain signal. The block supports the FFT length as a power of 2, in the range from 8 to 65, 536.

The Divide butterfly outputs by two parameter sets whether the FFT implements an overall 1/N scale factor by dividing the output of each butterfly multiplication by two. This adjustment keeps the output of the IFFT in the same amplitude range as its input. When you clear the Divide butterfly outputs by two parameter, the block avoids overflow by increasing the word length by 1 bit after each butterfly multiplication.

Conventionally, transceivers perform an FFT shift in the frequency domain. However, this method requires memory and introduces latency related to the size of the FFT. Instead, a transceiver can execute the same operation in the time domain by using the frequency shifting property of Fourier transforms. Shifting a function in one domain corresponds to a multiplication by a complex exponential function in the other domain. To reduce hardware resources and latency, this block performs the FFT shift by multiplying the time-domain samples by a complex exponential function.

These equations describe an FFT shift. The equation for an N-point FFT is

For an FFT shift of N/2 carriers in either direction, substitute $$k=k-\frac{N}{2}$$, resulting in

This equation simplifies to

Since $${\displaystyle \sum _{n=0}^{N-1}x(n)e^{-\frac{j2\pi nk}{N}}}$$ is equivalent to $$F[x(n)]$$, and $$e^{j\pi }=-1$$, this equation simplifies to

The final equation shows that an FFT shift in the time domain simplifies to multiplication by (-1)ⁿ. Therefore, the block implements the FFT shift by multiplying the time-domain samples by either +1 or –1.

This block down samples the maximum FFT length number of samples to FFT length number of samples. This block is optional and available only when the OFDM parameters source parameter is set to Input port. When OFDM parameters source is set to Property, the FFT length value provided in the block mask is considered as the maximum FFT length. So, there is no need to downsample the samples in this context.

For example, the block is operating with FFT length as 128 and the maximum FFT length is 2048. Here, the input is 2048 samples and it must be downsampled with respective to the FFT length 128. So, the block samples 1 sample for every 16 samples.

Cyclic prefix addition is the process of adding the last samples of an OFDM symbol as a prefix to each OFDM symbol. This figures shows CP addition for an OFDM symbol with Nfft samples and CP samples N_CP.

When the OFDM Modulator block operates through Input portselection, it uses the Maximum FFT length parameter to avoid multiple IFFTs.

The block captures output bits at valid cycles.

This figure shows a sample output and latency of the OFDM Modulator block when you set the OFDM parameters source parameter to Property and other parameters set with default block parameter values. The default input parameter FFTLen is set to 64, Insert DC null status is set to on, Number of left guard subcarriers and Number of left guard subcarriers are set to 6 and 5 respectively.

Here, the latency of the block is calculated using the formula, FFT length – (Number of left guard subcarriers + Number of right guard subcarriers + Insert DC null status) + Latency of IFFT block for the specified FFT length + FFT length + 15 (pipeline delays).

After calculation, the latency of the block is 305 clock cycles, as shown in the following figure.

This figure shows a sample output and latency of the block when you set the OFDM parameters source parameter to Input port. For example, the input port FFTLen is set to 64, Insert DC null status is set to on, numLgSc and numRgSc are set to 6 and 5 respectively, and Maximum FFT length parameter value is set to 128.

Here, the latency of the block is calculated using the formula, FFT length – (Number of left guard subcarriers + Number of right guard subcarriers + Insert DC null status) + FFT length + Latency of IFFT block for the specified maximum FFT length + Maximum FFT length – (Maximum FFT length/FFT length) + 26 (pipeline delays).

After calculation, the latency of the block is 575 clock cycles, as shown in the following figure.

The block accepts input only when the ready signal is 1 (high), and then it captures block parameters on the first cycle when the input valid signal is 1 (high).

The performance of the synthesized HDL code varies with your target and synthesis options. The input data type used for generating HDL code is fixdt(1,16,14).

This table shows the resource and performance data synthesis results when using the block with a default configuration. The generated HDL is targeted to Xilinx^® Zynq^®- 7000 ZC706 Evaluation Board. The design achieves a clock frequency of 283 MHz.