Guided Code Generation

Guided code generation using the HDL Workflow Advisor

Functions

`hdladvisor`	Display HDL Workflow Advisor
`hdlsetup`	Set up model parameters for HDL code generation
`hdlsetuptoolpath`	Set up system environment to access FPGA synthesis software

Model Checks

HDL Coder Checks in Model Advisor / HDL Code Advisor Overview

Check for global reset setting for Xilinx and Altera devices

Check algebraic loops

Simulink Configuration Parameters

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Code and Model Generation Settings

HDL Code Generation Top-Level Pane Overview

Target

Code Generation Output

Model Generation for HDL Code

Naming Options

Layout Options

RTL Style

Generate VHDL code for model references into a single library

Language-Specific Comments and Identifiers

Global Settings Overview

Language-Specific Identifiers

Language-Specific File Extensions

Code Generation Output

Comment in header

VHDL Architecture and Library Name

File Comment Customization

Generate Statement Labels

Topics

Getting Started with the HDL Workflow Advisor

Learn the basics of the HDL Workflow Advisor and how to run various tasks.

HDL Workflow Advisor Tasks

Describes HDL Workflow Advisor tasks.

HDL Code Generation and FPGA Synthesis Using Simulink HDL Workflow Advisor

Learn how to generate code and synthesize your design on the target hardware.

Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor

Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.

Run HDL Workflow with a Script

Export, import, or configure an HDL Workflow CLI command script.

Synthesis Objective to Tcl Command Mapping

Tool-specific Tcl commands that correspond to the HDL Workflow synthesis objectives

Getting Started with the HDL Workflow Command-Line Interface

This example shows how to use the HDL Workflow Advisor to run HDL workflows from the command-line and the 'Export to script' functionality.

Documentation