HDL Code Generation and FPGA Synthesis Using Simulink HDL Workflow Advisor

This example shows how you can use the HDL Workflow Advisor to generate HDL code and synthesize your design on a target Xilinx® FPGA. For this tutorial, you can use a simple up counter model that you created as a source for HDL code generation. The model simulates an up counter that counts from zero to a threshold value and then wraps back to zero. To learn how to create this model, see Create Simulink Model for HDL Code Generation.

Simple Up Counter Model

Open Script

Open this model to see a simple up counter. The model counts up from zero to a threshold value and then wraps back to zero. In this model, the threshold value is set to 15. You can change the threshold value by changing the value of the Constant block that is input to the count_threshold port. The Enable signal specifies whether the counter should count up or hold the previous value. The Enable signal is set to 1 which means that the counter counts upwards continuously.

open_system('hdlcoder_simple_up_counter.slx')
set_param('hdlcoder_simple_up_counter', 'SimulationCommand', 'Update')

About HDL Workflow Advisor

The HDL Workflow Advisor guides you through the stages of generating HDL code for a Simulink® subsystem and the FPGA design process, such as:

  • Checking the model for HDL code generation compatibility and automatically fixing incompatible settings.

  • Generation of HDL code, a test bench, and scripts to build and run the code and test bench.

  • Generation of cosimulation or SystemVerilog DPI test benches and code coverage (requires HDL Verifier™).

  • Synthesis and timing analysis through integration with third-party synthesis tools.

  • Back-annotation of the model with critical path information and other information obtained during synthesis.

  • Complete automated workflows for selected FPGA development target devices and the Simulink Real-Time™ FPGA I/O workflow, including FPGA-in-the-loop simulation.

Set Up Tool Path

If you do not want to synthesize your design, but want to generate HDL code, you do not have to set the tool path. In the HDL Workflow Advisor, on the Set Target > Set Target Device and Synthesis Tool step, leave the Synthesis tool setting to the default No Synthesis Tool Specified, and then run the workflow.

If you want to synthesize your design on a target platform, before you open the HDL Workflow Advisor and run the workflow, set up the path to your Synthesis tool. This example uses Xilinx Vivado, so you must have already installed Xilinx Vivado. To set the tool path, use the hdlsetuptoolpath function to point to an installed Xilinx Vivado 2019.1 executable. To learn about the latest supported tools, see HDL Language Support and Supported Third-Party Tools and Hardware.

hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath',...
 'C:\Xilinx\Vivado\2019.1\bin\vivado.bat');

Note

Optionally, you can use a different synthesis tool of your choice and follow this example. To set the path to that synthesis tool, use hdlsetuptoolpath.

Open the HDL Workflow Advisor

To start the HDL Workflow Advisor from a Simulink model,

  1. In the Apps tab, select HDL Coder. The HDL Code tab appears.

  2. Select the DUT Subsystem in your model, and make sure that this Subsystem name appears in the Code for option. To remember the selection, you can pin this option. Click Workflow Advisor.

When you open the HDL Workflow Advisor, the code generator can warn that the project folder is incompatible. To open the Advisor, select Remove slprj and continue.

In the HDL Workflow Advisor, the left pane lists the folders in the hierarchy. Each folder represents a group or category of related tasks. Expanding the folders shows available tasks in each folder. From the left pane, you can select a folder or an individual task. The HDL Workflow Advisor displays information about the selected folder or task in the right pane. The contents of the right pane depends on the selected folder or task. For some tasks, the right pane contains simple controls for running the task and a display area for status messages and other task results. For other tasks that involve setting code or test bench generation parameters, the right pane displays several parameter and option settings.

To learn more about each individual task, right-click that task, and select What's This?.

To learn more about the HDL Workflow Advisor window, see Getting Started with the HDL Workflow Advisor.

Generate HDL Code

  1. In the Set Target > Set Target Device and Synthesis Tool step, for Synthesis tool, select Xilinx Vivado and select Run This Task.

  2. In Set Target Frequency task, specify a Target Frequency that you want the design to achieve. For this example, you can set Target Frequency (MHz) to 200.

  3. Leave all settings to default and right-click the Check Sample Times task and select Run to Selected Task.

    By running the tasks in the Prepare Model For HDL Code Generation folder, the HDL Workflow Advisor checks the model for code generation compatibility.

    Note

    If running a task generates a warning, select Modify All, and rerun the task.

  4. To modify code generation options, use the tasks in Set Code Generation Options. For example, to customize the target HDL language and the target code generation folder, use the Set Basic Options task. After you make changes, click Apply.

  5. To generate code, right-click the Generate RTL Code and Testbench task, and select Run to Selected Task.

    Note

    If you want to generate an HDL test bench or a validation model, you can specify the corresponding settings in the Generate RTL Code and Testbench task. To specify additional test bench options, use the Set Testbench Options task.

Perform FPGA Synthesis and Analysis

  1. In the FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and Route task, clear Skip this task and click Apply.

  2. Right-click Annotate Model with Synthesis Result and select Run to Selected Task.

  3. View the annotated critical path in the model.

    Note

    If you select Intel Quartus Pro or Microsemi Libero SoC as the Synthesis tool, the Annotate Model with Synthesis Result task is not available. In this case, you can run the workflow to synthesis and then view the timing reports to see the critical path.

Run Workflow at Command Line with a Script

To run the HDL workflow at a command line, you can export the Workflow Advisor settings to a script. To export to script, in the HDL Workflow Advisor window, select File > Export to Script. In the Export Workflow Configuration dialog box, enter a file name and save the script.

The script is a MATLAB® file that you can run from the command line. You can modify the script directly or, import the script into the HDL Workflow Advisor, modify the tasks, and export the updated script. To learn more, see Run HDL Workflow with a Script.

See Also

| |

Related Topics

HDL Coder Documentation
Support