Programmatic Workflow

Command-line functions for code generation and configuration

Functions

Code Generation

`makehdl`	Generate HDL RTL code from model, subsystem, or model reference
`makehdltb`	Generate HDL test bench from model or subsystem

Configuration

`hdlsetup`	Set up model parameters for HDL code generation
`hdlsetuptoolpath`	Set up system environment to access FPGA synthesis software
`hdlset_param`	Set HDL-related parameters at model or block level
`hdlget_param`	Return value of specified HDL block-level parameter for specified block
`hdlsaveparams`	Save nondefault block- and model-level HDL parameters
`hdlrestoreparams`	Restore block- and model-level HDL parameters to model
`hdldispmdlparams`	Display HDL model parameters with nondefault values
`hdldispblkparams`	Display HDL block parameters with nondefault values

Properties

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Test Bench

`ClockHighTime`	Specify period, in nanoseconds, during which test bench drives clock input signals high (1)
`ClockLowTime`	Specify period, in nanoseconds, during which test bench drives clock input signals low (0)
`ForceClock`	Specify whether test bench forces clock input signals
`ForceClockEnable`	Specify whether test bench forces clock enable input signals
`ForceReset`	Specify whether test bench forces reset input signals
`GenerateCoSimBlock`	Generate HDL Cosimulation blocks for use in testing DUT
`GenerateCoSimModel`	Generate model containing HDL Cosimulation block for use in testing DUT
`GenerateSVDPITestbench`	Generate SystemVerilog DPI test bench
`HDLCodeCoverage`	Include HDL code coverage switches in generated test bench scripts
`HoldInputDataBetweenSamples`	Specify how long subrate signal values are held in valid state
`HoldTime`	Specify hold time for input signals and forced reset input signals
`IgnoreDataChecking`	Specify number of samples during which output data checking is suppressed
`InitializeTestBenchInputs`	Specify initial value driven on test bench inputs before data is asserted to DUT
`MultifileTestBench`	Divide generated test bench into helper functions, data, and HDL test bench code files
`SimulationLibPath`	Specify the path to the compiled Altera or Xilinx simulation libraries
`SimulationTool`	Simulator for which the tool generates build-and-run scripts for the test bench and optional code coverage
`SimulatorFlags`	Specify simulator flags to apply to generated compilation scripts
`TestBenchClockEnableDelay`	Define elapsed time in clock cycles between deassertion of reset and assertion of clock enable
`TestBenchDataPostFix`	Specify suffix added to test bench data file name when generating multifile test bench
`TestBenchPostFix`	Specify suffix to test bench name
`TestBenchReferencePostFix`	Specify text appended to names of reference signals generated in test bench code
`UseFileIOInTestBench`	Specify whether to use data files for reading and writing test bench stimulus and reference data
`FPToleranceStrategy`	Specify whether to check for floating-point tolerance based on relative error or ULP error
`FPToleranceValue`	Enter the tolerance value based on floating-point tolerance check setting

Script Generation

`EDAScriptGeneration`	Enable or disable generation of script files for third-party tools
`HDLCompileInit`	Specify text written to initialization section of compilation script
`HDLCompileTerm`	Specify text written to termination section of compilation script
`HDLCompileFilePostfix`	Specify postfix appended to file name for generated Mentor Graphics ModelSim compilation scripts
`HDLCompileVerilogCmd`	Specify command written to compilation script for Verilog files
`HDLCompileVHDLCmd`	Specify command written to compilation script for VHDL files
`HDLLintCmd`	Specify command written to HDL lint script
`HDLLintInit`	Specify HDL lint script initialization name
`HDLLintTerm`	Specify HDL lint script termination name
`HDLLintTool`	Select HDL lint tool for which HDL Coder generates scripts
`HDLSimCmd`	Specify command written to simulation script
`HDLSimInit`	Specify text written to initialization section of simulation script
`HDLSimFilePostfix`	Specify postfix appended to file name for generated Mentor Graphics ModelSim simulation scripts
`HDLSimTerm`	Specify text written to termination section of simulation script
`HDLSimViewWaveCmd`	Specify waveform viewing command written to simulation script
`HDLSynthCmd`	Specify command written to synthesis script
`HDLSynthFilePostfix`	Specify postfix appended to file name for generated synthesis scripts
`HDLSynthInit`	Specify text written to initialization section of synthesis script
`HDLSynthTerm`	Specify text written to termination section of synthesis script
`HDLSynthTool`	Select synthesis tool for which HDL Coder generates scripts

Examples and How To

Generate HDL Code from Simulink Model

Learn about the counter model and how to generate VHDL or Verilog^® code from models.

Obfuscate Generated HDL Code from Simulink Models

Learn how to obfuscate the generated VHDL^® or Verilog code from your model.

Set HDL Code Generation Options

Access HDL options in the Configuration Parameters dialog box and Model Explorer; Simulink Toolstrip, HDL Code context menu, and pointers to related information

Set and View HDL Model and Block Parameters

How to view or set the implementation parameters for a block

Add or Remove the HDL Configuration Component

Adding an HDL configuration component to make models more portable