2-D FIR filtering
Vision HDL Toolbox / Filtering
The Image Filter block performs two-dimensional finite impulse response (FIR) filtering on a pixel stream and supports the use of programmable filter coefficients.
This block uses a streaming pixel interface with a bus for
frame control signals. This interface enables the block to operate independently of image size
and format. The pixel ports on this block support single pixel streaming or
multipixel streaming. Single pixel streaming accepts and returns a single pixel value each clock
cycle. Multipixel streaming accepts and returns 4 or 8 pixels per clock cycle to support
high-frame-rate or high-resolution formats. Along with the pixel, the block accepts and returns
a pixelcontrol
bus that contains five control signals. The control signals
indicate the validity of each pixel and their location in the frame. For multipixel streaming,
one set of control signals applies to all four or eight pixels in the vector. To convert a frame
(pixel matrix) into a serial pixel stream and control signals, use the Frame
To Pixels block. For a full description of the interface, see Streaming Pixel Interface.
pixel
— Input pixel or multipixel vectorThis block supports single pixel streaming or multipixel streaming. For single pixel streaming, specify a single input pixel as a scalar intensity value. For multipixel streaming, specify a vector of four or eight pixel intensity values. For details of how to set up your model for multipixel streaming, see Filter Multipixel Video Streams.
This block does not support multicomponent streaming. To process multicomponent
streams, replicate the block for each component. The pixelcontrol
bus
for all components is identical, so you can connect a single bus to multiple replicated
blocks.
double
and single
data
types are supported for simulation, but not for HDL code generation.
Data Types: uint8
| uint16
| uint32
| int8
| int16
| int32
| fixed point
| Boolean
| double
| single
ctrl
— Control signals associated with pixel streampixelcontrol
busSpecify a pixelcontrol
bus that contains
five signals. The signals describe the validity of the pixel and its location in the frame. For
more information, see Pixel Control Bus.
For multipixel streaming, each vector of pixel values has one set of control signals.
Because the vector has only one valid
signal, the pixels in the
vector must be either all valid or all invalid. The hStart
and
vStart
signals apply to the pixel with the lowest index in the
vector. The hEnd
and vEnd
signals apply to the
pixel with the highest index in the vector.
Data Types: bus
coeff
— Filter coefficientsSpecify the filter coefficients as a 2-D matrix of numeric values. Each dimension of the matrix must have at least 2 elements, but no more than 64 elements.
double
and single
data
types are supported for simulation, but not for HDL code generation.
The block samples the values from the coeff port only at the start of a frame and ignores any changes within a frame.
To enable this port, set the Filter coefficients source
parameter to Input port
.
Data Types: single
| double
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| fixed point
pixel
— Output pixel or multipixel vectorThis block supports single pixel streaming or multipixel streaming. When using single pixel streaming, the block returns a single pixel as a scalar intensity value. When using multipixel streaming, the block returns a vector of intensity values. This vector is the same size as the input pixel vector. For details of how to set up your model for multipixel streaming, see Filter Multipixel Video Streams.
The output pixel data type is the same as the data type of the input pixels.
double
and single
data
types are supported for simulation, but not for HDL code generation.
Data Types: uint8
| uint16
| uint32
| int8
| int16
| int32
| fixed point
| Boolean
| double
| single
ctrl
— Control signals associated with pixel streampixelcontrol
busSpecify a pixelcontrol
bus that contains
five signals. The signals describe the validity of the pixel and its location in the frame. For
more information, see Pixel Control Bus.
For multipixel streaming, each vector of pixel values has one set of control signals.
Because the vector has only one valid
signal, the pixels in the
vector are either all valid or all invalid. The hStart
and
vStart
signals apply to the pixel with the lowest index in the
vector. The hEnd
and vEnd
signals apply to the
pixel with the highest index in the vector.
Data Types: bus
Filter coefficients source
— Source to provide filter coefficientsProperty
(default) | Input port
Select the source for specifying the filter coefficients.
Property
(default) — Use this value to
specify filter coefficients using the Filter coefficients
parameter.
Input port
— Use this value to specify
filter coefficients through the coeff input port.
Filter coefficients
— Coefficients of filter[ 1, 0; 0, -1 ]
(default) | matrixSpecify the filter coefficients as a matrix. Each dimension of the matrix must have at least 2 elements, but no more than 64 elements.
To enable this parameter, set the Filter coefficients
source parameter to Property
.
Padding method
— Method for paddingConstant
(default) | Replicate
| Symmetric
| None
Select one of these methods for padding the boundary of the input image. For more information about these methods, see Edge Padding.
Constant
— Interpret pixels outside the image frame
as having a constant value.
Replicate
— Repeat the value of pixels at the edge
of the image.
Symmetric
— Set the value of the padding pixels to
mirror the edge of the image.
None
— Exclude padding logic. The block does not set the pixels
outside the image frame to any particular value. This option reduces the hardware resources
used by the block and the blanking required between frames but affects the accuracy of the
output pixels at the edges of the frame. To maintain pixel stream timing, the output frame
is the same size as the input frame. However, to avoid using pixels calculated from
undefined padding values, mask off the KernelSize/2 pixels around the
edge of the frame for downstream operations. For details, see Increase Throughput with Padding None.
Padding value
— Value used to pad boundary of input image0
(default) | integerSpecify an integer to pad the boundary of the input image. The block casts this value to the same data type as the input pixel.
To enable this parameter, set the Padding method parameter to
Constant
.
Line buffer size
— Size of line buffer2048
(default) | integerSpecify a power of two that accommodates the number of active pixels in a single horizontal line.
If you specify a value that is not a power of two, the block uses the next largest power of two. The block allocates (N — 1)-by-Line buffer size memory locations to store the pixels. N represents the rows of the coefficient matrix.
Rounding mode
— Rounding mode for internal fixed-point calculationsFloor
(default) | Ceiling
| Convergent
| Nearest
| Round
| Zero
Select the rounding mode for internal fixed-point calculations as
Floor
, Ceiling
,
Convergent
, Nearest
,
Round
, and Zero
. For more
information about rounding modes, see Rounding Modes (DSP System Toolbox).
Saturate on integer overflow
— Overflow action for internal fixed-point calculationsoff
(default) | on
When you clear this parameter, fixed-point and integer values wrap around to zero when the value overflows what is representable with that data type. When you select this parameter, the value saturates at the maximum representable value.
Coefficients
— Filter coefficients data type selectionInherit: Same as first input
(default) | fixdt(1, 16, 0)
| <data type expression>
Select the method for determining the data type of the filter coefficients.
Click the Show data type assistant button to display the Data Type Assistant, which helps you set the data type of the Coefficients parameter. For details, see Specify Data Types Using Data Type Assistant (Simulink).
When converting the coefficients to the specified data type, the block rounds to the nearest representable value and saturates to the maximum value if the value exceeds the maximum value representable with the data type.
To enable this parameter, set the Filter coefficients
source parameter to Property
.
Output
— Output data type selectionInherit: Same as first input
(default) | Inherit: Inherit via internal rule
| fixdt(1, 16, 0)
| <data type expression>
Select the method for determining the data type of the output pixel.
Click the Show data type assistant button to display the Data Type Assistant, which helps you to set the data type of the Output parameter. For details, see Specify Data Types Using Data Type Assistant (Simulink).
Lock data type settings against changes by the fixed-point tools
— Lock data type settingsoff
(default) | on
Select this parameter to lock all data type settings of this block against changes by the Fixed-Point Tool and the Fixed-Point Advisor. For more information, see Lock the Output Data Type Setting (Fixed-Point Designer).
The block implements the 2-D FIR filter with a fully pipelined architecture. Each multiplier has two pipeline stages on each input and two pipeline stages on each output. The adder is a pipelined tree structure. HDL code generation uses symmetric, unity, or zero-value coefficients to reduce the number of multipliers.
When you use multipixel streaming, the block uses a single line memory and implements NumberOfPixels filter kernels in parallel. This increase in hardware resources is a trade off for increasing throughput compared to single-pixel streaming.
When you provide coefficients using the Filter coefficients
parameter, you can optimize the multipliers for HDL code generation by using a canonical
signed digit (CSD) representation or factored CSD representation. To use a CSD of factored CSD
representation, right-click the block, select HDL Code > HDL
Block Properties, and set the ConstMultiplierOptimization
parameter to csd
or fcsd
.
When you provide coefficients using the coeff port, the latency depends on the size of the filter coefficients. For an N-by-M coefficient matrix provided using the coeff port, the block generates NxM multipliers.
The latency of the block is the line buffer latency plus the
latency of the kernel calculation. The line buffer latency includes edge padding by default. The
latency of the padding operation depends on the size of the kernel. If edge padding is not
necessary for your design, you can reduce the latency by setting the Padding
method parameter to None
. When you use this option, the block
latency does not depend on your kernel size. To determine the exact latency for any
configuration of the block, measure the number of time steps between the input and output
control signals.
Note
When you use edge padding, use a horizontal blanking interval greater than twice the kernel width. This interval lets the block finish processing one line before it starts processing the next one, including adding padding pixels before and after the active pixels in the line. Standard streaming video formats use a horizontal blanking interval of about 25% of the frame width. This interval is much larger than the filters applied to each frame. When you disable edge padding, the horizontal blanking interval must be at least 12 cycles and is independent of the kernel size. If you are using a custom video format, set the horizontal blanking interval by using the Frame To Pixels block parameters. The horizontal blanking interval is equal to Total pixels per line – Active pixels per line or, equivalently, Front porch + Back porch. For more information, see Configure Blanking Intervals.
This block supports C/C++ code generation for Simulink® accelerator and rapid accelerator modes and for DPI component generation.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has a single, default HDL architecture.
ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
You cannot generate HDL code for this block if it is inside a Resettable Synchronous Subsystem (HDL Coder).
Frame To Pixels | visionhdl.ImageFilter
| 2-D FIR
Filter (Computer Vision Toolbox)