Histogram

Frequency distribution of pixel values in video stream

Library:
Vision HDL Toolbox / Statistics

Description

The Histogram block computes the frequency distribution of pixel values in a video stream. You can configure the number and size of the bins. The block provides a read interface for accessing each bin. The block keeps a running histogram until you reset the bin values.

Ports

This block uses a streaming pixel interface with a bus for frame control signals. This interface enables the block to operate independently of image size and format. All Vision HDL Toolbox™ blocks use the same streaming interface. The block accepts a scalar pixel value and a bus that contains five control signals. The control signals indicate the validity of each pixel and its location in the frame. To convert a frame (pixel matrix) into a pixel stream and control signals, use the Frame To Pixels block. For a full description of the interface, see Streaming Pixel Interface.

Input

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`pixel` — Single image pixel
scalar

Single image pixel, specified as an unsigned integer scalar value.

double and single data types are supported for simulation, but not for HDL code generation.

Data Types: single | double | uint | fixdt(0,N,0)

`ctrl` — Control signals associated with pixel stream
`pixelcontrol` bus

Specify a pixelcontrol bus that contains five signals. The signals describe the validity of the pixel and its location in the frame. For more information, see Pixel Control Bus.

Data Types: bus

`binAddr` — Bin number for reading histogram values
integer

The block captures this value each cycle that the readRdy output port is 1 (true). The data type is fixdt(0,N,0), N = 5,6,...,12. The word length must be log₂(Number of bins).

Data Types: fixdt(0,N,0)

`binReset` — Reset histogram bin values
scalar

A binReset value of 1 (true) triggers a RAM initialization sequence that resets the histogram bin values. Reset takes NumBins cycles to clear all locations. Input signals are ignored during this interval.

Data Types: Boolean

Output

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`readRdy` — Indicates histogram bins available for read
scalar

When readRdy is 1 (true), the histogram bins are ready to read. The block returns readRdy set to 1 (true) two cycles after the final pixel of a frame.

Data Types: Boolean

`hist` — Bin value corresponding to requested address
integer

Histogram bin value corresponding to the requested address, binAddr. The Data type parameter specifies the data type for this value.

Data Types: fixed point

`validOut` — Indicates that histogram value is valid
scalar

When validOut is 1 (true), the histogram bin value, hist, is valid.

Data Types: Boolean

Parameters

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`Number of bins` — Number of histogram bins
`256` (default) | power of 2 between `32` and `4096`

Choose the number of bins depending on the input word length (WL). If the number of bins is less than 2^WL, the block truncates the least-significant bits of each pixel. If the number of bins is greater than 2^WL, some bins are not used, and after you synthesize your design it will use more hardware resources than necessary.

`Data type` — Data type of histogram bin values
`Unsigned fixed point` (default) | `double` | `single`

Data type of histogram bin values.

double and single data types are supported for simulation, but not for HDL code generation.

`Word length` — Word length of histogram bins
`16` (default) | integer

Word length of the histogram bins. If a bin overflows, the count saturates and the block shows a warning.

Dependencies

This parameter applies when you set Data type to Unsigned fixed point.

Model Examples

Histogram Equalization

Use the Vision HDL Toolbox Histogram library block to implement histogram equalization.

Algorithms

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RAM Reset and Ready Sequence

Before sending the first input data, you must wait Number of bins cycles for the block to reset the RAM. This initial reset happens without asserting binReset.

You cannot read histogram bins and apply pixel data at the same time. To read the bin values, wait for the readRdy port to be 1 (true), and then apply each bin address of interest to the binAddr port. The block provides the corresponding histogram values on the hist port, with an accompanying validOut signal.

The histogram values persist and accumulate across frames until you assert binReset. At that time, the block takes Number of bins cycles to clear the RAM and be ready for new input. Other input signals are ignored during reset.

The diagram shows an overview of the reset sequence. vStart and vEnd are control signals in the pixelcontrol input bus.

The diagram shows the automatic startup reset, followed by a frame of video input. The read window starts when readRdy is asserted. The binReset signal initiates a bin reset. The next input frame is not applied until after the reset is complete.

The following diagram illustrates a bin read sequence. vEnd is a control signal in the pixelcontrol input bus. validOut indicates when the bin values on hist are available.

After the last pixel of a video frame, indicated by vEnd = true, the block asserts readRdy to show that the histogram is ready for reading. Two cycles after applying a bin address, the block provides the value of that bin on hist, with a corresponding valid signal. You can request the last bin address and assert binReset at the same time.

Latency

The block sets readRdy to true two cycles after receiving the last pixel of a frame. The input pixelcontrol bus indicates the last pixel of a frame by vEnd = true. While readRdy is true, the block captures binAddr requests on each cycle. The block provides the corresponding histogram bin values on hist two cycles later.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Restrictions

You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).

Documentation

Histogram

Description

Ports

Input

`pixel` — Single image pixel
scalar

`ctrl` — Control signals associated with pixel stream
`pixelcontrol` bus

`binAddr` — Bin number for reading histogram values
integer

`binReset` — Reset histogram bin values
scalar

Output

`readRdy` — Indicates histogram bins available for read
scalar

`hist` — Bin value corresponding to requested address
integer

`validOut` — Indicates that histogram value is valid
scalar

Parameters

`Number of bins` — Number of histogram bins
`256` (default) | power of 2 between `32` and `4096`

`Data type` — Data type of histogram bin values
`Unsigned fixed point` (default) | `double` | `single`

`Word length` — Word length of histogram bins
`16` (default) | integer

Dependencies

Model Examples

Histogram Equalization

Algorithms

RAM Reset and Ready Sequence

Latency

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Blocks

Objects

Functions

Vision HDL Toolbox Documentation

Support

Documentation

Histogram

Description

Ports

Input

pixel — Single image pixel scalar

ctrl — Control signals associated with pixel stream pixelcontrol bus

binAddr — Bin number for reading histogram values integer

binReset — Reset histogram bin values scalar

Output

readRdy — Indicates histogram bins available for read scalar

hist — Bin value corresponding to requested address integer

validOut — Indicates that histogram value is valid scalar

Parameters

Number of bins — Number of histogram bins 256 (default) | power of 2 between 32 and 4096

Data type — Data type of histogram bin values Unsigned fixed point (default) | double | single

Word length — Word length of histogram bins 16 (default) | integer

Dependencies

Model Examples

Histogram Equalization

Algorithms

RAM Reset and Ready Sequence

Latency

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Blocks

Objects

Functions

Vision HDL Toolbox Documentation

Support

`pixel` — Single image pixel
scalar

`ctrl` — Control signals associated with pixel stream
`pixelcontrol` bus

`binAddr` — Bin number for reading histogram values
integer

`binReset` — Reset histogram bin values
scalar

`readRdy` — Indicates histogram bins available for read
scalar

`hist` — Bin value corresponding to requested address
integer

`validOut` — Indicates that histogram value is valid
scalar

`Number of bins` — Number of histogram bins
`256` (default) | power of 2 between `32` and `4096`

`Data type` — Data type of histogram bin values
`Unsigned fixed point` (default) | `double` | `single`

`Word length` — Word length of histogram bins
`16` (default) | integer

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.