Bias
Add bias to input
- Library:
Simulink / Math Operations
HDL Coder / HDL Floating Point Operations
HDL Coder / Math Operations
Description
The Bias block adds a bias, or offset, to the input signal according to
Y = U + bias
where U is the block input and Y is the output.
Ports
Input
Port_1 — Input signal
scalar | vector
Input signal to which the bias is added to create the output signal.
Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point
Output
Port_1 — Output signal
scalar | vector
Output signal resulting from adding the bias to the input signal.
Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point
Parameters
Bias — Offset to add to the input signal
0.0 (default) | scalar | vector
Specify the value of the offset to add to the input signal.
Programmatic Use
Block Parameter:
Bias |
| Type: character vector |
| Values: real, finite |
Default:
'0.0' |
Saturate on integer overflow — Choose the behavior when integer overflow occurs
off (default) | on
| Action | Reasons for Taking This Action | What Happens for Overflows | Example |
|---|---|---|---|
|
Select this check box. |
Your model has possible overflow, and you want explicit saturation protection in the generated code. |
Overflows saturate to either the minimum or maximum value that the data type can represent. |
The maximum value that the |
|
Do not select this check box. |
You want to optimize efficiency of your generated code. You want to avoid overspecifying how a block handles out-of-range signals. For more information, see Troubleshoot Signal Range Errors. |
Overflows wrap to the appropriate value that is representable by the data type. |
The maximum value that the |
When you select this check box, saturation applies to every internal operation on the block, not just the output or result. Usually, the code generation process can detect when overflow is not possible. In this case, the code generator does not produce saturation code.
Programmatic Use
Block Parameter:
DoSatur |
| Type: character vector |
Value: 'off' |
'on' |
Default: 'off' |
Block Characteristics
Data Types |
|
Direct Feedthrough |
|
Multidimensional Signals |
|
Variable-Size Signals |
|
Zero-Crossing Detection |
|
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has a single, default HDL architecture.
| ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
| InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
| OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|