Divide
Divide one input by another
- Library:
Simulink / Math Operations
HDL Coder / HDL Floating Point Operations
HDL Coder / Math Operations
Description
The Divide block outputs the result of dividing its first input by its second. The inputs can be scalars, a scalar and a nonscalar, or two nonscalars that have the same dimensions. This block supports only complex input values at division ports when all ports have the same single or double data type.
The Divide block is functionally a Product block that has two block parameter values preset:
Multiplication —
Element-wise(.*)Number of Inputs —
*/
Setting nondefault values for either of those parameters can change a Divide block to be functionally equivalent to a Product block or a Product of Elements block.
Ports
Input
X — Input signal to multiply
scalar | vector | matrix | N-D array
Input signal to be multiplied with other inputs.
Dependencies
To enable one or more X ports, specify one or
more * characters for the Number of
inputs parameter.
Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point
÷ — Input signal to divide or invert
scalar | vector | matrix | N-D array
Input signal for division or inversion operations.
Dependencies
To enable one or more ÷ ports, specify one or
more / characters for the Number of
inputs parameter.
Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point
Port_1 — First input to multiply or divide
scalar | vector | matrix | N-D array
First input to multiply or divide, provided as a scalar, vector, matrix, or N-D array.
Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point
Port_N — Nth input to multiply or divide
scalar | vector | matrix | N-D array
Nth input to multiply or divide, provided as a scalar, vector, matrix, or N-D array.
Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point
Output
Port_1 — Output computed by multiplying, dividing, or inverting inputs
scalar | vector | matrix | N-D array
Output computed by multiplying, dividing, or inverting inputs.
Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point
Parameters
Main
Number of inputs — Control number of inputs and type of operation
*/ (default) | positive integer scalar | * or / for each input
port
Control two properties of the block:
The number of input ports on the block
Whether each input is multiplied or divided into the output
When you specify:
1or*or/The block has one input port. In element-wise mode, the block processes the input as described for the Product of Elements block. In matrix mode, if the parameter value is
1or*, the block outputs the input value. If the value is/, the input must be a square matrix (including a scalar as a degenerate case) and the block outputs the matrix inverse. See Element-Wise Mode and Matrix Mode for more information.Integer value > 1
The block has the number of inputs given by the integer value. The inputs are multiplied together in element-wise mode or matrix mode, as specified by the Multiplication parameter. See Element-Wise Mode and Matrix Mode for more information.
Unquoted string of two or more
*and/charactersThe block has the number of inputs given by the length of the character vector. Each input that corresponds to a
*character is multiplied into the output. Each input that corresponds to a/character is divided into the output. The operations occur in element-wise mode or matrix mode, as specified by the Multiplication parameter. See Element-Wise Mode and Matrix Mode for more information.
Programmatic Use
Block Parameter:
Inputs |
| Type: character vector |
Values:
'2' | '*' | '**' | '*/' | '*/*' |
... |
Default:
'*/' |
Multiplication — Element-wise (.*) or Matrix (*) multiplication
Element-wise(.*) (default) | Matrix(*)
Specify whether the block performs Element-wise(.*) or
Matrix(*) multiplication.
Programmatic Use
Block Parameter:
Multiplication |
| Type: character vector |
Values:
'Element-wise(.*)' | 'Matrix(*)' |
Default:
'Element-wise(.*)' |
Multiply over — All dimensions or specified dimension
All dimensions (default) | Specified dimension
Specify the dimension to multiply over as All dimensions, or
Specified dimension. When you select
Specified dimension, you can specify the
Dimension as 1 or
2.
Dependencies
To enable this parameter, set Number of inputs to * and Multiplication to Element-wise (.*).
Programmatic Use
Block Parameter: CollapseMode |
| Type: character vector |
Values: 'All dimensions' | 'Specified dimension' |
Default: 'All dimensions' |
Dimension — Dimension to multiply over
1 (default) | 2 | ... | N
Specify the dimension to multiply over as an integer less than or equal to the number of dimensions of the input signal.
Dependencies
To enable this parameter, set:
Number of inputs to
*Multiplication to
Element-wise (.*)Multiply over to
Specified dimension
Programmatic Use
Block Parameter: CollapseDim |
| Type: character vector |
Values:
'1' | '2' | ... |
Default: '1' |
Sample time — Specify sample time as a value other than -1
-1 (default) | scalar | vector
Specify the sample time as a value other than -1. For more information, see Specify Sample Time.
Dependencies
This parameter is not visible unless it is explicitly set to a value other than
-1. To learn more, see Blocks for Which Sample Time Is Not Recommended.
Programmatic Use
Block Parameter:
SampleTime |
| Type: character vector |
| Values: scalar or vector |
Default:
'-1' |
Signal Attributes
Require all inputs to have the same data type — Require that all inputs have the same data type
off (default) | on
Specify if input signals must all have the same data type. If you enable this parameter, then an error occurs during simulation if the input signal types are different.
Programmatic Use
Block Parameter:
InputSameDT |
| Type: character vector |
Values:
'off' | 'on' |
Default:
'off' |
Output minimum — Minimum output value for range checking
[] (default) | scalar
Lower value of the output range that Simulink® checks.
Simulink uses the minimum to perform:
Parameter range checking (see Specify Minimum and Maximum Values for Block Parameters) for some blocks.
Simulation range checking (see Specify Signal Ranges and Enable Simulation Range Checking).
Automatic scaling of fixed-point data types.
Optimization of the code that you generate from the model. This optimization can remove algorithmic code and affect the results of some simulation modes such as SIL or external mode. For more information, see Optimize using the specified minimum and maximum values (Embedded Coder).
Note
Output minimum does not saturate or clip the actual output signal. Use the Saturation block instead.
Programmatic Use
Block Parameter:
OutMin |
| Type: character vector |
Values: '[ ]'|
scalar |
Default: '[ ]' |
Output maximum — Maximum output value for range checking
[] (default) | scalar
Upper value of the output range that Simulink checks.
Simulink uses the maximum value to perform:
Parameter range checking (see Specify Minimum and Maximum Values for Block Parameters) for some blocks.
Simulation range checking (see Specify Signal Ranges and Enable Simulation Range Checking).
Automatic scaling of fixed-point data types.
Optimization of the code that you generate from the model. This optimization can remove algorithmic code and affect the results of some simulation modes such as SIL or external mode. For more information, see Optimize using the specified minimum and maximum values (Embedded Coder).
Note
Output maximum does not saturate or clip the actual output signal. Use the Saturation block instead.
Programmatic Use
Block Parameter:
OutMax |
| Type: character vector |
Values: '[ ]'|
scalar |
Default: '[ ]' |
Output data type — Specify the output data type
Inherit: Inherit via internal
rule (default) | Inherit: Inherit via back propagation | Inherit: Same as first input | double | single | int8 | uint8 | int16 | uint16 | int32 | uint32 | int64 | uint64 | fixdt(1,16) | fixdt(1,16,0) | fixdt(1,16,2^0,0) | <data type expression>
Choose the data type for the output. The type can be inherited, specified
directly, or expressed as a data type object such as
Simulink.NumericType. For more information, see
Control Signal Data Types.
When you select an inherited option, the block behaves as follows:
Inherit: Inherit via internal rule— Simulink chooses a data type to balance numerical accuracy, performance, and generated code size, while taking into account the properties of the embedded target hardware. If you change the embedded target settings, the data type selected by the internal rule might change. For example, if the block multiplies an input of typeint8by a gain ofint16andASIC/FPGAis specified as the targeted hardware type, the output data type issfix24. IfUnspecified (assume 32-bit Generic), in other words, a generic 32-bit microprocessor, is specified as the target hardware, the output data type isint32. If none of the word lengths provided by the target microprocessor can accommodate the output range, Simulink software displays an error in the Diagnostic Viewer.It is not always possible for the software to optimize code efficiency and numerical accuracy at the same time. If the internal rule doesn’t meet your specific needs for numerical accuracy or performance, use one of the following options:
Specify the output data type explicitly.
Use the simple choice of
Inherit: Same as input.Explicitly specify a default data type such as
fixdt(1,32,16)and then use the Fixed-Point Tool to propose data types for your model. For more information, seefxptdlg(Fixed-Point Designer).To specify your own inheritance rule, use
Inherit: Inherit via back propagationand then use a Data Type Propagation block. Examples of how to use this block are available in the Signal Attributes library Data Type Propagation Examples block.
Inherit: Inherit via back propagation— Use data type of the driving block.Inherit: Same as first input— Use data type of first input signal.
Programmatic Use
Block Parameter:
OutDataTypeStr |
| Type: character vector |
Values: 'Inherit:
Inherit via internal rule |
'Inherit: Same as first input' |
'Inherit: Inherit via back
propagation' | 'double'
| 'single' | 'int8' |
'uint8' |
'int16' |
'uint16' |
'int32' |
'uint32' |
'int64' |
'uint64' |
'fixdt(1,16)' |
'fixdt(1,16,0)' |
'fixdt(1,16,2^0,0)' |
'<data type
expression>' |
Default: 'Inherit:
Inherit via internal rule' |
Lock output data type setting against changes by the fixed-point tools — Prevent fixed-point tools from overriding Output data type
off (default) | on
Select this parameter to prevent the fixed-point tools from overriding the Output data type you specify on the block. For more information, see Use Lock Output Data Type Setting (Fixed-Point Designer).
Programmatic Use
Block Parameter:
LockScale |
| Type: character vector |
Values:
'off' | 'on' |
Default:
'off' |
Integer rounding mode — Rounding mode for fixed-point operations
Floor (default) | Ceiling | Convergent | Nearest | Round | Simplest | Zero
Select the rounding mode for fixed-point operations. You can select:
CeilingRounds positive and negative numbers toward positive infinity. Equivalent to the MATLAB®
ceilfunction.ConvergentRounds number to the nearest representable value. If a tie occurs, rounds to the nearest even integer. Equivalent to the Fixed-Point Designer™
convergentfunction.FloorRounds positive and negative numbers toward negative infinity. Equivalent to the MATLAB
floorfunction.NearestRounds number to the nearest representable value. If a tie occurs, rounds toward positive infinity. Equivalent to the Fixed-Point Designer
nearestfunction.RoundRounds number to the nearest representable value. If a tie occurs, rounds positive numbers toward positive infinity and rounds negative numbers toward negative infinity. Equivalent to the Fixed-Point Designer
roundfunction.SimplestChooses between rounding toward floor and rounding toward zero to generate rounding code that is as efficient as possible.
ZeroRounds number toward zero. Equivalent to the MATLAB
fixfunction.
For more information, see Rounding (Fixed-Point Designer).
Block parameters always round to the nearest representable value. To control the rounding of a block parameter, enter an expression using a MATLAB rounding function into the mask field.
Programmatic Use
Block Parameter:
RndMeth |
| Type: character vector |
Values:
'Ceiling' | 'Convergent' | 'Floor' | 'Nearest' | 'Round' | 'Simplest' |
'Zero' |
Default:
'Floor' |
Saturate on integer overflow — Method of overflow action
off (default) | on
Specify whether overflows saturate or wrap.
| Action | Rationale | Impact on Overflows | Example |
|---|---|---|---|
|
Select this check box ( |
Your model has possible overflow, and you want explicit saturation protection in the generated code. |
Overflows saturate to either the minimum or maximum value that the data type can represent. |
The maximum value that the |
|
Do not select this check box ( |
You want to optimize efficiency of your generated code. You want to avoid overspecifying how a block handles out-of-range signals. For more information, see Troubleshoot Signal Range Errors. |
Overflows wrap to the appropriate value that is representable by the data type. |
The maximum value that the |
When you select this check box, saturation applies to every internal operation on the block, not just the output, or result. Usually, the code generation process can detect when overflow is not possible. In this case, the code generator does not produce saturation code.
Programmatic Use
Block Parameter: SaturateOnIntegerOverflow |
| Type: character vector |
Values:
'off' | 'on' |
Default: 'off' |
Model Examples
Block Characteristics
Data Types |
|
Direct Feedthrough |
|
Multidimensional Signals |
|
Variable-Size Signals |
|
Zero-Crossing Detection |
|
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
These conditions may yield different results between simulation and the generated code:
The Divide block inputs contain a
NaNorinfvalueThe Divide block generates
NaNorinfduring execution
This difference is due to the nonfinite NaN or
inf values. In such cases, inspect your model
configuration and eliminate the conditions that produce NaN
or inf.
The Simulink Coder™ build process provides efficient code for matrix inverse and division operations. This table describes the benefits and when each benefit is available.
| Benefit | Small Matrices (2-by-2 to 5-by-5) | Medium Matrices (6-by-6 to 20-by-20) | Large Matrices (larger than 20-by-20) |
|---|---|---|---|
| Faster code execution time, compared to R2011a and earlier releases | Yes | No | Yes |
| Reduced ROM and RAM usage, compared to R2011a and earlier releases | Yes, for real values | Yes, for real values | Yes, for real values |
| Reuse of variables | Yes | Yes | Yes |
| Dead code elimination | Yes | Yes | Yes |
| Constant folding | Yes | Yes | Yes |
| Expression folding | Yes | Yes | Yes |
| Consistency with MATLAB Coder results | Yes | Yes | Yes |
For blocks that have three or more inputs of different dimensions, the code might include an extra buffer to store temporary variables for intermediate results.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
Note
When you deploy the generated HDL code onto the target hardware, make sure
that you set the signed integer division rounds to
parameter in the Hardware Implementation pane of the
Configuration Parameters dialog box to Zero or
Floor.
To perform an HDL-optimized divide operation, connect a Product block to a Divide block in reciprocal mode.
Default Mode
The Divide block is the same as a Product block
with Number of Inputs set to */.
| Architecture | Parameters | Description |
|---|---|---|
Linear
default | None | Generate a divide (/) operator in the HDL
code. |
ShiftAdd | UsePipelines | Perform divide operations on fixed-point types by using a non-restoring division algorithm that performs multiple shift and add operations to compute the quotient. This architecture provides improved accuracy compared to the Newton-Raphson approximation method. When you
use this architecture, to achieve a higher maximum clock
frequency on the target FPGA device, leave the
UsePipelines HDL block property to
|
Reciprocal Mode
When Number of Inputs is set to /, the
Divide block is in reciprocal mode.
This block has multi-cycle implementations that introduce additional latency in the generated code. To see the added latency, view the generated model or validation model. See Generated Model and Validation Model (HDL Coder).
In reciprocal mode, the Divide block has the HDL block implementations described in the following table.
| Architectures | Parameters | Additional cycles of latency | Description |
|---|---|---|---|
defaultLinear | None | 0 | When you compute a reciprocal, use the HDL divide ( |
ReciprocalRsqrtBasedNewton | Iterations | Signed input: Unsigned
input: | Use the iterative Newton method. Select this option to optimize area. The default value for The recommended value for |
ReciprocalRsqrtBasedNewtonSingleRate | Iterations | Signed input: ( Unsigned input: ( | Use the single rate pipelined Newton method. Select this option to optimize speed, or if you want a single rate implementation. The
default value for The
recommended value for |
ShiftAdd | UsePipelines | Signed input: (Input wordlength + 4) Unsigned input: (Input wordlength + 4) | Perform reciprocal operation on a fixed-point input by using a non-restoring division algorithm that performs multiple shift and add operations to compute the reciprocal. This architecture provides improved accuracy compared to the Newton-Raphson approximation method. When you use this architecture, to achieve a higher
maximum clock frequency on the target FPGA device, leave the
UsePipelines HDL block property to
|
The Newton-Raphson iterative method:
ReciprocalRsqrtBasedNewton and
ReciprocalRsqrtBasedNewtonSingleRate implement
the Newton-Raphson method with:
| General | |
|---|---|
| ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
| ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
| DSPStyle | Synthesis attributes for multiplier mapping. The default is
Use this property with:
|
| InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
| OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
| LatencyStrategy | To enable this property, set HDL architecture to
|
| CustomLatency | To enable this property, set HDL architecture to
|
| Native Floating Point | |
|---|---|
| HandleDenormals | Specify whether you want HDL Coder to insert additional logic to handle denormal numbers in your design.
Denormal numbers are numbers that have magnitudes less than the smallest floating-point
number that can be represented without leading zeros in the mantissa. The default is
|
| NFPCustomLatency | To specify a value, set
LatencyStrategy to |
| MantissaMultiplyStrategy | Specify how to implement the mantissa multiplication operation during code generation.
By using different settings, you can control the DSP usage on the target FPGA device.
The default is |
| DivisionAlgorithm | Specify whether to use the Radix-2 or Radix-4 algorithm to perform the floating-point division. The Radix-2 mode offers a trade-off between latency and frequency. The Radix-4 mode offers a trade-off between latency and resource usage. For more information, see DivisionAlgorithm (HDL Coder). |
To see the latency calculation for fixed-point types with Divide and Reciprocal blocks, at the MATLAB command prompt, enter:
HDLMathLib
This block does not support code generation for division with complex signals.
When you use the Divide block in reciprocal mode, the following restrictions apply:
When you use fixed-point types, the input and output must be scalar. To use vector inputs, specify the
Matharchitecture and input a floating-point value.Only the
Zerorounding mode is supported.You must select the Saturate on integer overflow option on the block.
For the Divide block, only the Zero and
Simplest rounding modes are supported.