Simulink Cosimulation

HDL cosimulation with Simulink®

Blocks

HDL Cosimulation Cosimulate HDL design by connecting Simulink with HDL simulator
To VCD FileGenerate value change dump (VCD) file

Apps

Cosimulation WizardGenerate a cosimulation block or System object from existing HDL files

Functions

expand all

nclaunchStart and configure Cadence Incisive simulators for use with HDL Verifier software
vsimStart and configure ModelSim for use with HDL Verifier
hdlsimulinkLoad instantiated HDL module for cosimulation with Cadence Incisive and Simulink
vsimulinkLoad instantiated HDL module for cosimulation with ModelSim and Simulink
breakHdlSimExecute stop command in HDL simulator from MATLAB
pingHdlSimBlock cosimulation until HDL simulator is ready
tclHdlSimExecute Tcl command in Incisive or ModelSim simulator

Topics

Startup and Connection

Set Up for HDL Cosimulation

To cosimulate your HDL code with a MATLAB® or Simulink design, you must first:

Supported EDA Tools and Hardware

List of supported third-party EDA software and FPGA boards.

Start HDL Simulator for Cosimulation in Simulink

Set up the connection between the HDL simulator and Simulink.

TCP/IP Socket Ports

Provides some direction for choosing TCP/IP socket ports.

Cross-Network Cosimulation

Provides instructions for performing cosimulation across a local network.

Test Bench

Simulink as a Test Bench

Provides an introduction to the process for integrating HDL Verifier™ blocks into a Simulink design.

Create a Simulink Cosimulation Test Bench

The steps to code and run a Simulink-as-test bench cosimulation for use with the HDL Verifier software.

Verify HDL Module with Simulink Test Bench

The steps for setting up an HDL Verifier session that uses Simulink to verify a simple VHDL® model.

Verify Raised Cosine Filter Design Using Simulink

Provides instruction in using the Cosimulation Wizard to create a Simulink model for cosimulation.

Verification of Generated HDL Code with Cosimulation Test Bench (requires HDL Coder license)

Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder)

Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.

Automatic Verification of Generated HDL Code from Simulink

Verify generated HDL code using a generated cosimulation model.

Component Algorithm

Component Simulation with Simulink

Provides an introduction to the process for integrating blocks into a Simulink design.

Create Simulink Model for Component Cosimulation

Provides a high-level view of the steps involved in coding and running a Simulink-as-component cosimulation for use with the software.

Cosimulation with Simulink

HDL Cosimulation

The HDL Verifier software consists of MATLAB functions, a MATLAB System object™, and a library of Simulink blocks, all of which establish communication links between the HDL simulator and MATLAB or Simulink.

Performing Cosimulation

Next steps after you generate a function or block representing your HDL module.

Prepare to Import HDL Code for Cosimulation

Prepare for cosimulation and choose whether to cosimulate your HDL code as a function, System object, or block.

Import HDL Code for HDL Cosimulation Block

Generate a Simulink block to cosimulate your HDL code.

Run a Simulink Cosimulation Session

Run your test bench or algorithm, including the cosimulation of your HDL module.

HDL Simulator Interaction

Simulation Timescales

The representation of simulation time differs significantly between the HDL simulator and Simulink.

Clock, Reset, and Enable Signals

You can create rising-edge or falling-edge clocks, resets, or clock enable signals that apply internal stimuli to your model under cosimulation.

Simulation Speed Improvement Tips

Provides suggestions for optimizing your cosimulation performance.

Supported Data Types

If your HDL application needs to send HDL data to a MATLAB function, you may first need to convert the data to a type supported by MATLAB and the HDL Verifier software.

Race Conditions in HDL Simulators

Describes ways to avoid race conditions in hardware cosimulations with MATLAB and Simulink software.

Recording Signal State Transitions for Post-Processing

Add a Value Change Dump (VCD) File

A value change dump (VCD) file logs changes to variable values, such as the values of signals, in a file during a simulation session.

Visually Compare Simulink Signals with HDL Signals

Guides you through the basic steps for adding a To VCD File block to a Simulink model for use with cosimulation.

Featured Examples

Verify Viterbi Decoder Using HDL Cosimulation

Verify Viterbi Decoder Using HDL Cosimulation

Use HDL Verifier™ in conjunction with Mentor Graphics ModelSim®/QuestaSim® or Cadence Incisive®/Xcelium® to verify HDL code for a fixed-point Viterbi decoder.

Open Example
Timescales: Absolute, Relative and Automatic

Timescales: Absolute, Relative and Automatic

Illustrates the various Timescale settings within the HDL Cosimulation block and explains how these affect the timing relationship of Simulink® and the HDL simulator. We use a simple Verilog parity check model to show the timing relationship of Simulink and the HDL simulator (ModelSim® or Incisive®) used for cosimulation.

Open Model
Frame-based Scrambler Using Communications Toolbox™

Frame-based Scrambler Using Communications Toolbox™

Illustrates the validation of an HDL implementation of a 6-order scrambler. A scrambler is used in communication systems to randomize transitions in the transmitted signal by shuffling the bits. One purpose of scrambling is to reduce the length of strings of 0s or 1s in a transmitted signal, since a long string of 0s or 1s may cause transmission synchronization problems. Scrambling may also be used as a cheap encryption technique. This example consists of two models. The first model (scrambler_frame) validates the HDL implementation and the second model (scrambler_fsk) uses the HDL scrambler as part of a communication channel.

Batch Mode Cosimulation of Manchester Receiver

Batch Mode Cosimulation of Manchester Receiver

Illustrates using MATLAB® to start HDL simulator in batch mode and performing cosimulation with Simulink® using the HDL Verifier™ HDL Cosimulation block.

Manchester Receiver (Absolute Time Mode)

Manchester Receiver (Absolute Time Mode)

Verification of a Manchester encoder using HDL Verifier with Simulink. Manchester encoding is a simple modulation scheme that converts baseband digital data to an encoded waveform with no DC component. The most widely known application of this technique is Ethernet.

Manchester Receiver Using Communications Toolbox

Manchester Receiver Using Communications Toolbox

Verification of a Manchester encoder. Manchester encoding is a simple modulation scheme that converts baseband digital data to an encoded waveform with no DC component. The most widely known application of this technique is Ethernet.

Open Model
Manchester Receiver Using Multiple Cosimulation Blocks

Manchester Receiver Using Multiple Cosimulation Blocks

Simulates a digital receiver of Manchester encoded data. Manchester encoding is a simple modulation scheme that converts baseband digital data to an encoded waveform with no DC component. The most widely known application of this technique is Ethernet.

Manchester Receiver Using Mixed Design (Verilog and VHDL)

Manchester Receiver Using Mixed Design (Verilog and VHDL)

Verification of a Manchester encoder using mixed HDL languages, VHDL and Verilog. Manchester encoding is a simple modulation scheme which converts baseband digital data into an encoded waveform with no DC component. The most widely known application of this technique is Ethernet.

Sobel Edge Detection Algorithm with Computer Vision Toolbox

Sobel Edge Detection Algorithm with Computer Vision Toolbox

And explains the "Top-Down" design methodology that is applied to Sobel Edge Detection algorithm. The Sobel Edge Detection algorithm is a popular yet simple edge detection algorithm and is the focus of this example. With this example you will learn: How Simulink® allows you to design a digital signal processing (DSP) algorithm at a system level.

Relating HDL Clocks and Resets with Simulink Sample Times

Relating HDL Clocks and Resets with Simulink Sample Times

Illustrates the relationship of Simulink® sample times to HDL clocks and resets by using the HDL Verifier™ to cosimulate a simple synchronous Verilog parity check module. The example also contains the following: Explains how delta-time iterations in the HDL simulator (ModelSim® or Incisive®) may affect cosimulation results

Open Model

HDL Verifier Documentation

Support