HDL Cosimulation
Cosimulate HDL design by connecting Simulink with HDL simulator
- Library:
HDL Verifier / For Use with Cadence Incisive
HDL Verifier / For Use with Mentor Graphics ModelSim
Description
The HDL Cosimulation block cosimulates a hardware component by applying input signals to and reading output signals from an HDL model under simulation in the HDL simulator. You can use this block to model a source or sink device by configuring the block with input or output ports only.
You can configure these options on the block:
Mapping of the input and output ports of the block to correspond with signals (including internal signals) of an HDL module. You must specify a sample time for each output port. You can optionally specify a data type for each output port.
Type of communication and communication settings used to exchange data between simulators.
The timing relationship between units of simulation time in Simulink® and the HDL simulator.
Rising-edge or falling-edge clocks to apply to your model. You can specify the period for each clock signal.
Tcl commands to run before and after the simulation.
Compatibility with Simulink Code Generation
This block participates in HDL code generation with HDL Coder™. The coder generates an interface to your manually written or legacy HDL code. It does not participate in C code generation with Simulink Coder™.
Ports
The ports shown on the block correspond with signals from your HDL design running in the HDL simulator. You can add and remove ports, and configure their data types and sample times, by changing the block parameters. The Ports tab displays the HDL signals that correspond to the ports. You can add, remove, and change the order of the ports. Use the Auto Fill button to fill the table via a port information request to the HDL simulator. This request returns port names and information from your HDL design running in the HDL simulator. See “Get Signal Information from HDL Simulator” for a detailed description of this feature.
All signals that you specify when you configure the HDL Cosimulation block must have read/write access in the HDL simulator. Refer to the HDL simulator product documentation for details.
When you import VHDL® signals from the HDL simulator, HDL Verifier™ returns the signal names in all capitals.
Input
HDL_input_port_name — Signal passed from Simulink to HDL simulator
scalar | vector
The ports on the block correspond with ports on your HDL design. Add or remove ports on the Ports tab.
Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | Fixed-point
Output
HDL_output_port_name — Signal passed from HDL simulator to Simulink
scalar | vector
The ports on the block correspond with ports on your HDL design. Add or remove ports on the Ports tab.
Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | Fixed-point
Parameters
Ports
Enable direct feedthrough — Work around algebraic loop warnings
true (default) | false
Eliminates the one output-sample delay difference between the cosimulation and Simulink that occurs when your model contains purely combinational paths. Clear this check box if the HDL Cosimulation block is in a feedback loop and generates algebraic loop warnings or errors. When you simulate a sequential circuit that has a register on the data path, specifying direct feedthrough does not affect the timing of that data path.
Full HDL Name — Signal path name
string
Specify the signal path name using the HDL simulator path name syntax. For example,
manchester.samp for Incisive® HDL simulators. The signal can be at any level of the HDL
design hierarchy. The HDL Cosimulation block port
corresponding to the signal is labeled with this name.
For rules on specifying port and module path names in Simulink, see “Specify HDL Signal/Port and Module Paths for Cosimulation”.
You can copy signal path names directly from the HDL simulator wave window and paste them into the Full HDL Name field. Use the Path.Name view and not Db::Path.Name view. After pasting a signal path name into Full HDL Name, click Apply to complete the paste operation and update the signal list.
I/O Mode — Port direction
Input | Output
To add a bidirectional port, add the port to the list twice, as both input and output.
Input — HDL signals that Simulink drives. Simulink deposits values on the specified HDL simulator signal at the specified sample rate.
Note
When you define a block input port, make sure that only one source is set up to drive input to that signal. For example, avoid defining an input port that has multiple instances. If multiple sources drive input to a single signal, your simulation model produces unexpected results.
Output — HDL signals that Simulink reads. For output signals, you must specify an explicit sample time. You can also specify the data type, but the width must match the width of the signal in HDL. For details on specifying a data type, see the Data Type and Fraction Length parameters.
Simulink signals do not have a tristate semantic because there is no 'Z' value. To interface with bidirectional signals, connect to the input and enable signals of both the output driver and the output signal of the input driver. This approach leaves the actual tristate buffer in HDL, where resolution functions can handle interfacing with other tristate buffers.
Sample Time — Time between reading samples on an output port
1 (default) | integer
Time interval between consecutive samples applied to an output port.
Simulink deposits an input port signal on an HDL simulator signal at the specified sample rate. Conversely, Simulink reads an output port signal from a specified HDL simulator signal at the specified sample rate.
In general, Simulink handles port sample periods as follows:
If you connect an input port to a signal that has an explicit sample period, based on forward propagation, Simulink applies that rate to the port.
If you connect an input port to a signal that does not have an explicit sample period, Simulink assigns a sample period that is equal to the least common multiple (LCM) of all identified input port sample periods in the model.
After Simulink sets the input port sample periods, it applies user-specified output sample times to all output ports. You must specify an explicit sample time for each output port.
The exact interpretation of the output port sample time depends on the settings of the Timescales parameters of the HDL Cosimulation block. See also Simulation Timescales.
Dependencies
To enable this parameter, set I/O Mode to Output.
Data Type — Data type for output signal
Inherit (default) | Fixedpoint | Double | Single
Select Inherit to automatically determine the data type. The block checks that the inherited word length matches the word length queried from the HDL simulator. If they do not match, Simulink generates an error message. For example, if you connect a Signal Specification block to an output, Inherit forces the data type specified by the Signal Specification block onto the output port.
If Simulink cannot determine the data type of the signal connected to the output port, it queries the HDL simulator for the data type of the port. As an example, if the HDL simulator returns the VHDL data type STD_LOGIC_VECTOR for a signal of size N bits, the data type ufixN is forced on the output port. The implicit fraction length is 0.
You can also assign an explicit data type, with optional Fraction Length. By explicitly assigning a data type, you can force fixed-point data types on output ports of the HDL Cosimulation block. For example, for an 8-bit output port, setting the Sign to Signed and setting the Fraction Length to 5 forces the data type to sfix8_En5. You cannot force width. The width is always inherited from the HDL simulator.
Dependencies
To enable this parameter, set I/O Mode to Output.
The Data Type and Fraction Length properties apply only to the following types of HDL signals:
VHDL signals of any logic type, such as
STD_LOGICorSTD_LOGIC_VECTORVerilog® signals of
wireorregtype
Sign — Sign component of output data type
Unsigned (default) | Signed
Sign designation for explicit output port data type.
Dependencies
To enable this parameter, set I/O Mode to Output, and set Data Type to Fixedpoint.
Fraction Length — Number of fractional bits in output data type
integer
Size, in bits, of the fractional part of a fixed-point output signal. For example, for an 8-bit output port, setting the Sign to Signed and setting the Fraction Length to 5 forces the data type to sfix8_En5. You cannot force width; the width is always inherited from the HDL simulator.
Dependencies
To enable this parameter, set I/O Mode to Output, and Data Type property to Fixedpoint.
The Data Type and Fraction Length properties apply only to the following types of HDL signals:
VHDL signals of any logic type, such as
STD_LOGICorSTD_LOGIC_VECTORVerilog signals of
wireorregtype
Clocks
Create optional rising-edge and falling-edge clocks that apply stimuli to your cosimulation model. The scrolling list displays HDL clocks that drive values to the HDL signals that you are modeling, using the deposit method. The clock signals must be single-bit signals. Vector signals are not supported. For instructions on adding and editing clock signals, see Creating Optional Clocks with the Clocks Pane of the HDL Cosimulation Block.
Full HDL Name — Signal path name
string
Specify each clock as a signal path name, using the HDL simulator path name syntax. For example: /manchester/clk or manchester.clk.
For information about and requirements for path specifications in Simulink, see “Specify HDL Signal/Port and Module Paths for Cosimulation”.
You can copy signal path names directly from the HDL simulator wave window and paste them into the Full HDL Name field. Use the Path.Name view and not Db::Path.Name view. After pasting a signal path name into Full HDL Name, click Apply to complete the paste operation and update the signal list.
Active Clock Edge — HDL clock edge used to sample signals
Rising (default) | Falling
Select Rising or Falling to specify either a rising-edge clock or a falling-edge clock.
Period — Clock period
2 (default) | integer
To specify an explicit clock period, enter a sample time equal to or greater than two resolution units (ticks).
If the clock period is not an even integer, Simulink cannot create a 50% duty cycle. Instead, the HDL Verifier software creates the falling edge at clockperiod/2 (rounded down to the nearest integer).
Timescales
Choose a timing relationship between Simulink and the HDL simulator, either manually or automatically. These parameters specify a correspondence between one second of Simulink time and some quantity of HDL simulator time. This quantity of HDL simulator time can be expressed in one of the following ways:
Relative timing relationship (Simulink seconds correspond to an HDL simulator-defined tick interval)
Absolute timing relationship (Simulink seconds correspond to an absolute unit of HDL simulator time)
For more information on calculating relative and absolute timing modes, see Defining the Simulink and HDL Simulator Timing Relationship.
For detailed information on the relationship between Simulink and the HDL simulator during cosimulation, and on the operation of relative and absolute timing modes, see Simulation Timescales.
Automatically determine timescale at start of simulation — When to calculate automatic timescale
true (default) | false
If you select this option, HDL Verifier calculates the timescale when you start the Simulink simulation. If this option is not selected, click Determine Timescale Now to calculate the timescale immediately without starting a simulation. Alternatively, you can manually select a timescale. For guidance through the automatic timescale calculation, see Specify Timing Relationship Automatically.
1 second in Simulink corresponds to {} in the HDL simulator — Timing relationship between Simulink and HDL simulator
integer and time units
This parameter consists of a Time value and a TimeUnit value.
To configure relative timing mode for a cosimulation:
Verify that
Tick, the default setting for TimeUnit, is selected. If it is not, then select it from the list on the right.Enter a scale factor in the Time text box on the left. The default scale factor is 1.
To configure absolute timing mode for a cosimulation:
Set TimeUnit to a unit of absolute time:
fs(femtoseconds),ps(picoseconds),ns(nanoseconds),us(microseconds),ms(milliseconds), ors(seconds).Enter a scale factor in the Time text box on the left. The default scale factor is 1.
Connection
Connection mode — Connection between Simulink and HDL simulator
Full Simulation (default) | Confirm Interface Only | No Connection
Type of connection between Simulink and the HDL simulator.
Full Simulation: Confirm interface and run HDL simulation.Confirm Interface Only: Connect to the HDL simulator and check for signal names, dimensions, and data types, but do not run HDL simulation. During Simulink simulation, there is no contact with the HDL simulator.No Connection: Do not communicate with the HDL simulator. The HDL simulator does not need to be started.
HDL simulator is running on this computer — Same host for HDL simulator and Simulink
true (default) | false
When both applications run on the same computer, you can choose shared memory or TCP sockets for the communication channel between the applications. If you do not select this option, only TCP/IP socket mode is available, and the Connection method list becomes unavailable.
Connection method — Connection between HDL simulator and Simulink
Socket (default) | Shared memory
Socket: Simulink and the HDL simulator communicate via a designated TCP/IP socket. TCP/IP socket mode is more versatile. You can use it for single-system and network configurations. This option offers the greatest scalability. For more on TCP/IP socket communication, see TCP/IP Socket Ports.Shared memory: Simulink and the HDL simulator communicate via shared memory. Shared memory communication provides optimal performance and is the default mode of communication.
Dependencies
This parameter shows when you select HDL Simulator is running on this computer.
Host name — HDL simulator host machine
string
This parameter applies if you run Simulink and the HDL simulator on different computers.
Port number or service — Socket port number
string
Indicate a valid TCP socket port number or service for your computer system, if you are not using shared memory. For information on choosing TCP socket ports, see TCP/IP Socket Ports.
Show connection info on icon — Add connection parameters on block icon
true (default) | false
When you select this option, the HDL Cosimulation block icon displays the current communication parameter settings. If you select shared memory, the icon displays SharedMem. If you select TCP socket communication, the icon displays Socket and displays the host name and port number in the format hostname:port.
This information can help you distinguish between multiple HDL Cosimulation blocks, where each block is communicating to a different instance of the HDL simulator.
Simulation
Time to run HDL simulator before cosimulation starts — Offset that aligns Simulink with HDL simulator
integer and time unit
Specifies the amount of time to run the HDL simulator before beginning simulation in Simulink. Specifying this time properly aligns the signal of the Simulink block and the HDL signal so that they can be compared and verified directly without additional delays.
This setting consists of a PreRunTime value and a PreRunTimeUnit value.
PreRunTime: Any valid time value. The default is 0.
PreRunTimeUnit: Specifies the units of time for PreRunTime.
Ticksmsusnspsfs
Pre-simulation Tcl commands — Commands to run in HDL simulator before cosimulation
string
The cosimulation tool executes these commands in the HDL simulator, before simulating the HDL component of your Simulink model. If you enter multiple commands on one line, append each command with a semicolon (;), the standard Tcl concatenation operator.
For example, use this parameter to generate a one-line echo command to confirm that a simulation is running, or a complex script that performs an extensive simulation initialization and startup sequence. You cannot use these commands to change simulation state.
You can specify any valid Tcl command. The Tcl command you specify cannot include commands that load an HDL simulator project or modify simulator state. For example, the character vector cannot include commands such as start, stop, or restart (for ModelSim®) or run, stop, or reset (for Incisive).
Post-simulation Tcl commands — Commands to run in HDL simulator after cosimulation
string
The cosimulation tool executes these commands in the HDL simulator, after simulating the HDL component of your Simulink model.
You can specify any valid Tcl command. The Tcl command you specify cannot include commands that load an HDL simulator project or modify simulator state. For example, the string cannot include commands such as start, stop, or restart (for ModelSim) or run, stop, or reset (for Incisive).
Note
After each ModelSim simulation, the simulator takes time to update the coverage result. To prevent the potential conflict between this process and the next cosimulation session, add a short pause between each successive simulation.
Extended Capabilities
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. You can generate HDL code for cosimulation blocks used with Mentor Graphics® ModelSim or Cadence Incisive®.
Each of the HDL Cosimulation blocks cosimulates a hardware component by applying input signals to, and reading output signals from, an HDL model that executes under an HDL simulator. See Generate a Cosimulation Model (HDL Coder).
For information about timing, latency, data typing, frame-based processing, and other issues when setting up an HDL cosimulation, see Define HDL Cosimulation Block Interface.
You can use an HDL Cosimulation block with HDL Coder to generate an interface to your manually written or legacy HDL code. When an HDL Cosimulation block is included in a model, the coder generates a VHDL or Verilog interface, depending on the selected target language.
When the target language is VHDL, the generated interface includes:
An entity definition. The entity defines ports (input, output, and clock) corresponding in name and data type to the ports configured on the HDL Cosimulation block. Clock enable and reset ports are also declared.
An RTL architecture including a component declaration, a component configuration declaring signals corresponding to signals connected to the HDL Cosimulation ports, and a component instantiation.
Port assignment statements as required by the model.
When the target language is Verilog, the generated interface includes:
A module defining ports (input, output, and clock) corresponding in name and data type to the ports configured on the HDL Cosimulation block. The module also defines clock enable and reset ports, and
wiredeclarations corresponding to signals connected to the HDL Cosimulation ports.A module instance.
Port assignment statements as required by the model.
Before initiating code generation, check that the model meets the requirements for code generation. To check the requirements for code generation, select the Debug tab, and then click Update Model.
This block has a single, default HDL architecture.
For implementation parameter descriptions, see Customize Black Box or HDL Cosimulation Interface (HDL Coder).