Automatic Verification of Generated HDL Code from Simulink

The automatic verification feature integrates verification as part of the workflow for HDL cosimulation using the HDL Workflow Advisor. During this workflow, Simulink® generates a test bench model for HDL cosimulation. This test bench model compares the generated HDL DUT outputs (coming through the HDL Cosimulation block) with the original Simulink block outputs. The automatic verification step automatically runs this test bench. This step returns pass/fail information depending if the outputs of the HDL DUT match the output of original Simulink block in the test bench.

  1. Open HDL Workflow Advisor for your model.

  2. Step 1.1, select Generic ASIC/FPGA.

  3. Run all steps under 2, Prepare Model For HDL Code Generation.

  4. At step 3.1.5, Set Testbench Options, select Cosimulation model. Then set Simulation tool to either Mentor Graphics ModelSim or Cadence Incisive for your HDL simulator.

  5. At Step 3.2, Generate RTL Code and Testbench, select Generate testbench. This selection causes Step 3.3 to appear.

  6. At step 3.3, click Run This Task. The HDL Workflow Advisor and HDL Verifier™ verify the generated HDL using cosimulation between the HDL Simulator and the Simulink test bench. Any relevant status messages are displayed in the status window in the HDL Workflow Advisor.

HDL Verifier Documentation

Support