Verification with FPGA Hardware

Connect an FPGA board with MATLAB^® and Simulink^® for verification and debug of hardware designs

These features provide connections between your FPGA board and your simulations in Simulink or MATLAB.

FPGA-in-the-loop (FIL) enables you to run a Simulink or MATLAB simulation that is synchronized with an HDL design running on an Intel^®, Microsemi^®, or Xilinx^® FPGA board.
FPGA data capture is a way to observe signals from your design while the design is running on the FPGA. It captures a window of signal data from the FPGA, based on your configuration and trigger settings, and returns the data to MATLAB or Simulink.
MATLAB AXI master provides access to live on-board memory locations from MATLAB. You must include the MATLAB AXI master IP in your FPGA design.

To use these features, you must download a hardware support package for your FPGA board. See Download FPGA Board Support Package.

FPGA-in-the-Loop
Test designs in real hardware
FPGA Data Capture
Capture signal data from live FPGA
MATLAB AXI Master
Access AXI slave memory on FPGA board from MATLAB
Custom FPGA Board Definition
Create board definition files for FPGA verification projects

Documentation