MATLAB AXI Master

Access AXI slave memory on FPGA board from MATLAB®

Access on-board memory locations from MATLAB, using the MATLAB AXI master IP in your FPGA design, and the aximaster object. The object connects to the IP over JTAG, PCI Express or Ethernet cables, and allows read and write commands to slave memory locations from the MATLAB command line.

To use this feature, you must download a hardware support package for your FPGA board. More documentation for this feature is included with the support package installation. See support package documentation:

For information on downloading support packages, see Download FPGA Board Support Package.

Topics

Set Up for MATLAB AXI Master

High-level steps for accessing memory on an FPGA board from MATLAB.

Featured Examples

Access FPGA External Memory Using MATLAB as AXI Master

Access FPGA External Memory Using MATLAB as AXI Master

Use MATLAB as AXI Master to access the external DDR memories connected to the FPGA. In the FPGA, there is a Xilinx DDR memory controller instantiated for accessing the DDR memories. This memory controller provides an AXI4 slave interface for read and write operations by other components on the FPGA. The MATLAB as AXI Master feature provides an AXI master component that can be used to access any AXI slave IPs in the FPGA.

IP Core Generation Workflow With Ethernet Based MATLAB as AXI Master: Arrow DECA MAX 10 FPGA Evaluation Kit

IP Core Generation Workflow With Ethernet Based MATLAB as AXI Master: Arrow DECA MAX 10 FPGA Evaluation Kit

Uses Ethernet based MATLAB as AXI Master IP from HDL Verifier™ to access the HDL Coder™ generated registers. MATLAB as AXI Master provides access to FPGA registers from MATLAB directly. The FPGA design is implemented on the Arrow DECA MAX 10 FPGA evaluation kit.

HDL Verifier Documentation

Support