HDL Reciprocal

Calculate reciprocal with Newton-Raphson approximation method

Library

HDL Coder / Math Operations

Description

The HDL Reciprocal block uses the Newton-Raphson iterative method to compute the reciprocal of the block input. The Newton-Raphson method uses linear approximation to successively find better approximations to the roots of a real-valued function.

The reciprocal of a real number $a$ is defined as a zero of the function:

$f (x) = \frac{1}{x} - a$

HDL Coder™ chooses an initial estimate in the range $0 < x_{0} < \frac{2}{a}$ as this is the domain of convergence for the function.

To successively compute the roots of the function, specify the Number of iterations parameter in the Block Parameters dialog box. The process is repeated as:

$x_{i + 1} = x_{i} - \frac{f (x_{i})}{f' (x_{i})} = x_{i} + (x_{i} - a x_{i}^{2}) = x_{i} . (2 - a x_{i})$

$f' (x)$ is the derivative of the function $f (x)$ .

Following table shows comparison of simulation behavior of HDL Reciprocal with Math Reciprocal block:

Math Reciprocal	HDL Reciprocal
Computes the reciprocal as 1/N by using the HDL divide operator (/) to implement the division.	Uses the Newton-Raphson iterative method. The block computes an approximate value of reciprocal of the block input and can yield different simulation results compared to the Math Reciprocal block. To match the simulation results with the Math Reciprocal block, increase the number of iterations for the HDL Reciprocal block.

Math Reciprocal

HDL Reciprocal

Computes the reciprocal as 1/N by using the HDL divide operator (/) to implement the division.

Uses the Newton-Raphson iterative method. The block computes an approximate value of reciprocal of the block input and can yield different simulation results compared to the Math Reciprocal block.

To match the simulation results with the Math Reciprocal block, increase the number of iterations for the HDL Reciprocal block.

Parameters

Number of iterations: Number of Newton-Raphson iterations. The default is 3.

Ports

The block has the following ports:

Input

Supported data types: Fixed-point, integer (signed or unsigned), double, single
Minimum bit width: 2
Maximum bit width: 128

Output

Input data type	Output data type
double	double
single	single
built-in integer	built-in integer
built-in fixed-point	built-in fixed-point
`fi` (value, 0, word_length, fraction_length)	`fi` (value, 0, word_length, word_length–fraction_length–1)
`fi` (value, 1, word_length, fraction_length)	`fi` (value, 1, word_length, word_length–fraction_length–2)

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has multi-cycle implementations that introduce additional latency in the generated code. To see the added latency, view the generated model or validation model. See Generated Model and Validation Model.

Architecture Additional cycles of latency Description

Architecture	Additional cycles of latency	Description
`ReciprocalNewton` (default)	`Iterations` + 1	Use the multirate implementation of the iterative Newton method. Select this option to optimize area. The default value for `Iterations` is 3. The recommended value for `Iterations` is from 2 through 10. If `Iterations` is outside the recommended range, HDL Coder displays a message.
`ReciprocalNewtonSingleRate`	(`Iterations` * 2) + 1	Use the single rate pipelined Newton method. Select this option to optimize speed, or if you want a single rate implementation. The default value for `Iterations` is 3. The recommended value for `Iterations` is between 2 and 10. If `Iterations` is outside the recommended range, the coder displays a message.

ReciprocalNewton (default)

Iterations + 1

Use the multirate implementation of the iterative Newton method. Select this option to optimize area.

The default value for Iterations is 3.

The recommended value for Iterations is from 2 through 10. If Iterations is outside the recommended range, HDL Coder displays a message.

ReciprocalNewtonSingleRate

(Iterations * 2) + 1

Use the single rate pipelined Newton method. Select this option to optimize speed, or if you want a single rate implementation.

The default value for Iterations is 3.

The recommended value for Iterations is between 2 and 10. If Iterations is outside the recommended range, the coder displays a message.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline.

Documentation

HDL Reciprocal

Library

Description

Parameters

Ports

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

HDL Coder Documentation

Support

Documentation

HDL Reciprocal

Library

Description

Parameters

Ports

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

HDL Coder Documentation

Support

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.