Validation and Verification for System Development

An approach to validating and verifying system development is the V-model.

V-Model for System Development

The V-model is a representation of system development that highlights verification and validation steps in the system development process. The left side of the ‘V’ identifies steps that lead to code generation, including system specification and detailed software design. The right side of the V focuses on the verification and validation of steps cited on the left side, including software and system integration.

Depending on your application and its role in the process, you might focus on one or more of the steps called out in the V-model or repeat steps at several stages of the V-model. Code generation technology and related products provide tooling that you can apply to the V-model for system development. For more information about how you can apply MathWorks^® code generation technology and related products to the V-model process, see:

Types of Simulation and Prototyping in the V-Model

Use the V-model for system development for different types of simulation and prototyping, such as rapid simulation, system simulation, rapid prototyping, and rapid prototyping on target hardware. This table compares the types of simulation and prototyping identified on the left side of the V-model diagram shown in V-Model for System Development.

	Simulation	Rapid Simulation	System Simulation, Rapid Prototyping	Rapid Prototyping on Target Hardware
Purpose	Test and validate functionality of concept model	Refine, test, and validate functionality of concept model in nonreal time	Test new ideas and research	Refine and calibrate design during development process
Execution hardware	Development computer	Development computer Standalone executable runs outside of MATLAB^® and Simulink^® environments	PC or nontarget hardware	Embedded computing unit (ECU) or near-production hardware
Code efficiency and I/O latency	Not applicable	Not applicable	Less emphasis on code efficiency and I/O latency	More emphasis on code efficiency and I/O latency
Ease of use and cost	Can simulate component (algorithm or controller) and environment (or plant) Normal mode simulation in Simulink enables you to access, display, and tune data during verification Can accelerate Simulink simulations	Easy to simulate models of hybrid dynamic systems that include components and environment models Ideal for batch or Monte Carlo simulations Can repeat simulations with varying data sets, interactively or programmatically by using scripts, without rebuilding the model Can connect to Simulink to monitor signals and tune parameters	Might require custom real-time simulators and hardware Might be done with inexpensive, off-the-shelf PC hardware and I/O cards	Might use existing hardware for less expense and more convenience

Types of In-the-Loop Testing in the V-Model

This table compares types of in-the-loop testing for verification identified on the right side of the V-model diagram shown in V-Model for System Development.

	SIL Simulation	PIL Simulation on Embedded Hardware	PIL Simulation on Instruction Set Simulator	HIL Simulation
Purpose	Verify component source code	Verify component object code	Verify component object code	Verify system functionality
Fidelity and accuracy	Two options: Same source code as target, but might have numerical differences Changes source code to emulate word sizes, but is bit accurate for fixed-point math	Same object code Bit accurate for fixed-point math Cycle accurate because code runs on hardware	Same object code Bit accurate for fixed-point math Might not be cycle accurate	Same executable code Bit accurate for fixed-point math Cycle accurate Use real and emulated system I/O
Execution platforms	Development computer	Target hardware	Development computer	Target hardware
Ease of use and cost	Desktop convenience Executes only in Simulink Reduces hardware cost	Executes on desktop or test bench Uses hardware — process board and cables	Desktop convenience Executes on development computer with Simulink and integrated development environment (IDE) Reduces hardware cost	Executes on test bench or in a lab Uses hardware — processor, embedded computer unit (ECU), I/O devices, and cables
Real-time capability	Not real time	Not real time (between samples)	Not real time (between samples)	Hard real time

Code Generation Goal Summary

These tables list goals that you might have, as you apply code generation technology, and where to find guidance on how to meet those goals.

You can open and run the examples linked below and generate code.

Document and Validate Requirements

Goals	Related Product Information	Examples
Capture requirements in a document, spreadsheet, data base, or requirements management tool	Simulink Report Generator Third-party vendor tools such as Microsoft^® Word, Microsoft Excel^®, raw HTML, or IBM^® Rational^® DOORS^®
Associate requirements documents with objects in concept models Generate a report on requirements associated with a model	Requirements Management Interface (Simulink Requirements) Bidirectional tracing in Microsoft Word, Microsoft Excel, HTML, and IBM Rational DOORS	`slvnvdemo_fuelsys_docreq`
Include requirements links in generated code	Review and Maintain Requirements Links (Simulink Requirements)	`rtwdemo_requirements`
Trace model elements and subsystems to generated code and vice versa	Code Tracing	`rtwdemo_hyperlinks`
Verify, refine, and test concept model in non real time on a development computer	Model Architecture and Design Model Architecture and Design Simulation Acceleration	Air-Fuel Ratio Control System with Stateflow Charts
Run standalone rapid simulations Run batch or Monte-Carlo simulations Repeat simulations with varying data sets, interactively or programmatically with scripts, without rebuilding the model Tune parameters and monitor signals interactively Simulate models for hybrid dynamic systems that include components and an environment or plant that requires variable-step solvers and zero-crossing detection	Accelerate, Refine, and Test Hybrid Dynamic System on Host Computer by Using RSim System Target File External Mode Simulations for Parameter Tuning and Signal Monitoring	Run Rapid Simulations Over Range of Parameter Values Run Batch Simulations Without Recompiling Generated Code Use MAT-Files to Feed Data to Inport Blocks for Rapid Simulations
Distribute simulation runs across multiple computers	Simulink Test MATLAB Parallel Server Parallel Computing Toolbox

Develop System Specification

Goals	Related Product Information	Examples
Produce design artifacts for algorithms that you develop in MATLAB code for reviews and archiving	MATLAB Report Generator
Produce design artifacts from Simulink and Stateflow^® models for reviews and archiving	System Design Description (Simulink Report Generator)	`rtwdemo_codegenrpt`
Add one or more components to another environment for system simulation Refine a component model Refine an integrated system model Verify functionality of a model in nonreal time Test a concept model	Deploy Algorithm Model for Real-Time Rapid Prototyping
Schedule generated code	Absolute and Elapsed Time Computation Time-Based Scheduling and Code Generation Asynchronous Events	Time-Based Scheduling Example Models
Specify function boundaries of system	Subsystems	`rtwdemo_atomic` `rtwdemo_ssreuse` `rtwdemo_filepart` `rtwdemo_exporting_functions`
Specify components and boundaries for design and incremental code generation	Component-Based Modeling Component-Based Modeling	`rtwdemo_mdlreftop`
Specify function interfaces so that external software can compile, build, and invoke the generated code	Data and Function Configuration	`rtwdemo_configinterface` `rtwdemo_configdefaults` `rtwdemo_fcnprotoctrl` `rtwdemo_cppclass`
Manage data packaging in generated code for integrating and packaging data	Data and Function Configuration	`rtwdemo_ssreuse` `rtwdemo_mdlreftop` `rtwdemo_configinterface`
Generate and control the format of comments and identifiers in generated code	Configure Code Comments Construction of Generated Identifiers	`rtwdemo_comments` `rtwdemo_symbols`
Create a zip file that contains generated code files, static files, and dependent data to build generated code in an environment other than your host computer	Relocate Code to Another Development Environment	`rtwdemo_buildinfo`
Export models for validation in a system simulator using shared libraries	Package Generated Code as Shared Libraries	`rtwdemo_shrlib`
Refine component and environment model designs by rapidly iterating between algorithm design and prototyping Verify whether a component can adequately control a physical system in non-real time Evaluate system performance before laying out hardware, coding production software, or committing to a fixed design Test hardware	Deployment Deployment
Generate code for rapid prototyping	Generate Modular Function Code for Nonvirtual Subsystems	`rtwdemo_counter` `rtwdemo_counter_msvc` `rtwdemo_async`
Generate code for rapid prototyping in hard real time, using PCs	Simulink Real-Time	Create and Run Real-Time Application from Simulink Model (Simulink Real-Time)
Generate code for rapid prototyping in soft real time, using PCs	Simulink Desktop Real-Time	`sldrtex_vdp` (and others)

Develop Detailed Software Design

Goals	Related Product Information	Examples
Refine a model design for representation and storage of data in generated code	Data Access for Prototyping and Debugging Data Representation and Access
Select code generation features for deployment	Run-Time Environment Configuration Run-Time Environment Configuration Sharing Utility Code AUTOSAR Code Generation	`rtwdemo_counter` `rtwdemo_counter_msvc` `rtwdemo_async` AUTOSAR Workflow Samples (AUTOSAR Blockset)
Specify target hardware settings	Run-Time Environment Configuration Run-Time Environment Configuration	`rtwdemo_targetsettings`
Design model variants	Define, Configure, and Activate Variants Variant Systems
Specify fixed-point algorithms in Simulink, Stateflow, and the MATLAB language subset for code generation	Parameter Data Types in the Generated Code Fixed-Point Code Generation Support (Fixed-Point Designer)	`rtwdemo_fixpt1` Air-Fuel Ratio Control System with Fixed-Point Data
Convert a floating-point model or subsystem to a fixed-point representation	Iterative Fixed-Point Conversion in Simulink (Fixed-Point Designer)	`fxpdemo_fpa`
Iterate to obtain an optimal fixed-point design, using autoscaling	Parameter Data Types in the Generated Code	`fxpdemo_feedback`
Create or rename data types specifically for your application	Control Data Type Names in Generated Code	`rtwdemo_udt`
Control the format of identifiers in generated code	Construction of Generated Identifiers	`rtwdemo_symbols`
Specify how signals, tunable parameters, block states, and data objects are declared, stored, and represented in generated code	Organize Parameter Data into a Structure by Using Struct Storage Class	`rtwdemo_cscpredef`
Create a data dictionary for a model	What Is a Data Dictionary?	`rtwdemo_configinterface`
Relocate data segments for generated functions and data using `#pragmas` for calibration or data access	Control Data and Function Placement in Memory by Inserting Pragmas	`rtwdemo_memsec`
Assess and adjust model configuration parameters based on the application and an expected run-time environment	Model Configuration Model Configuration	Generate Code Using Simulink® Coder™ Generate Code Using Embedded Coder®
Check a model against basic modeling guidelines	Check Your Model Using the Model Advisor	`rtwdemo_advisor1`
Add custom checks to the Simulink Model Advisor	Create Model Advisor Checks (Simulink Check)	Create and Deploy a Model Advisor Custom Configuration (Simulink Check)
Check a model against custom standards or guidelines	Check Your Model Using the Model Advisor
Check a model against industry standards and guidelines (MathWorks Advisory Board (MAB), IEC 61508, IEC 62304, ISO 26262, EN 50128 and DO-178)	Standards, Guidelines, and Block Usage Check Model Compliance (Simulink Check)	`rtwdemo_iec61508`
Obtain model coverage for structural coverage analysis such as MCDC	Simulink Coverage
Prove properties and generate test vectors for models	Simulink Design Verifier™	`sldvdemo_cruise_control` `sldvdemo_cruise_control_verification`
Generate reports of models and software designs	MATLAB Report Generator Simulink Report Generator System Design Description (Simulink Report Generator)	`rtwdemo_codegenrpt`
Conduct reviews of your model and software designs with coworkers, customers, and suppliers who do not have Simulink available	Create Model Web Views (Simulink Report Generator)	Compare and Merge Simulink Models Containing Stateflow
Refine the concept model of your component or system Test and validate the model functionality in real time Test the hardware Obtain real-time profiles and code metrics for analysis and sizing based on your embedded processor Assess the feasibility of the algorithm based on integration with the environment or plant hardware	Deployment Deployment Code Execution Profiling Static Code Metrics	`rtwdemo_sil_topmodel`
Generate source code for your models, integrate the code into your production build environment, and run it on existing hardware	Code Generation Code Generation	`rtwdemo_counter` `rtwdemo_counter_msvc` `rtwdemo_fcnprotoctrl` `rtwdemo_cppclass` `rtwdemo_async` AUTOSAR Workflow Samples (AUTOSAR Blockset)
Integrate existing externally written C or C++ code with your model for simulation and code generation	Block Authoring and Simulation Integration External Code Integration	`rtwdemos`, select Model Architecture and Design > External Code Integration
Generate code for on-target rapid prototyping on specific embedded microprocessors and IDEs	Deploy Generated Component Software to Application Target Platforms	In `rtwdemo_vxworks`

Generate Application Code

Goals	Related Product Information	Examples
Optimize generated ANSI^® C code for production (for example, disable floating-point code, remove termination and error handling code, and combine code entry points into single functions)	Performance Performance	`rtwdemos`, select Performance
Optimize code for a specific run-time environment, using specialized function libraries	Code Replacement Code Replacement Code Replacement Customization	Optimize Generated Code By Developing and Using Code Replacement Libraries - Simulink®
Control the format and style of generated code	Model Configuration Parameters: Code Style	`rtwdemo_parentheses`
Control comments inserted into generated code	Model Configuration Parameters: Comments	`rtwdemo_comments`
Enter special instructions or tags for postprocessing by third-party tools or processes	Customize Post-Code-Generation Build Processing	`rtwdemo_buildinfo`
Include requirements links in generated code	Review and Maintain Requirements Links (Simulink Requirements)	`rtwdemo_requirements`
Trace model blocks and subsystems to generated code and vice versa	Code Tracing Standards, Guidelines, and Block Usage	`rtwdemo_comments` `rtwdemo_hyperlinks`
Integrate existing externally written code with code generated for a model	Block Authoring and Simulation Integration Code Integration	`rtwdemos`, select Model Architecture and Design > External Code Integration
Verify generated code for MISRA C^® ^[a] and other run-time violations	MISRA C Guidelines Polyspace Bug Finder Polyspace Code Prover
Protect the intellectual property of component model design and generated code Generate a binary file (shared library)	Reference Protected Models from Third Parties Package Generated Code as Shared Libraries
Generate a MEX-file S-function for a model or subsystem so that it can be shared with a third-party vendor	Generate S-Function from Subsystem
Generate a shared library for a model or subsystem so that it can be shared with a third-party vendor	Package Generated Code as Shared Libraries
Test generated production code with an environment or plant model to verify a conversion of the model to code	Software-in-the-Loop Simulation	Test Generated Code with SIL and PIL Simulations
Create an S-function wrapper for calling your generated source code from a model running in Simulink	Write Wrapper S-Function and TLC Files
Set up and run SIL tests on your host computer	Software-in-the-Loop Simulation	Test Generated Code with SIL and PIL Simulations
^[a] MISRA^® and MISRA C are registered trademarks of MISRA Ltd., held on behalf of the MISRA Consortium.

Integrate and Verify Software

Goals	Related Product Information	Examples
Integrate existing externally written C or C++ code with a model for simulation and code generation	Block Authoring and Simulation Integration Code Integration	`rtwdemos`, select Model Architecture and Design > External Code Integration
Connect to data interfaces for generated C code data structures	Data Exchange Interfaces Data Exchange Interfaces	`rtwdemo_capi` `rtwdemo_asap2`
Control the generation of code interfaces so that external software can compile, build, and invoke the generated code	Data and Function Configuration	`rtwdemo_fcnprotoctrl` `rtwdemo_cppclass`
Export virtual and function-call subsystems	Generate Component Source Code for Export to External Code Base	`rtwdemo_exporting_functions`
Include target-specific code	Code Replacement Code Replacement Code Replacement Customization	Optimize Generated Code By Developing and Using Code Replacement Libraries - Simulink®
Customize and control the build process	Build Process Customization	`rtwdemo_buildinfo`
Create a zip file that contains generated code files, static files, and dependent data to build the generated code in an environment other than your host computer	Relocate Code to Another Development Environment	`rtwdemo_buildinfo`
Integrate software components as a complete system for testing in the target environment	Target Environment Verification
Generate source code for integration with specific production environments	Code Generation Code Generation	`rtwdemo_async` AUTOSAR Workflow Samples (AUTOSAR Blockset)
Integrate code for a specific run-time environment, using specialized function libraries	Code Replacement Code Replacement Code Replacement Customization	Optimize Generated Code By Developing and Using Code Replacement Libraries - Simulink®
Enter special instructions or tags for postprocessing by third-party tools or processes	Customize Post-Code-Generation Build Processing	`rtwdemo_buildinfo`
Integrate existing externally written code with code generated for a model	Block Authoring and Simulation Integration External Code Integration	`rtwdemos`, select Model Architecture and Design > External Code Integration
Connect to data interfaces for the generated C code data structures	Data Exchange Interfaces Data Exchange Interfaces	`rtwdemo_capi` `rtwdemo_asap2`
Schedule the generated code	Timers Time-Based Scheduling Event-Based Scheduling	Time-Based Scheduling Example Models
Verify object code files in a target environment	Software-in-the-Loop Simulation	Test Generated Code with SIL and PIL Simulations
Set up and run PIL tests on your target system	Processor-in-the-Loop Simulation	Test Generated Code with SIL and PIL Simulations Configure Processor-In-The-Loop (PIL) for a Custom Target Create a Target Communication Channel for Processor-In-The-Loop (PIL) Simulation See the list of `supported hardware` for the Embedded Coder^® product on the MathWorks Web site, and then find an example for the related product of interest

Integrate, Verify, and Calibrate System Components

Goals	Related Product Information	Examples
Integrate the software and its microprocessor with the hardware environment for the final embedded system product Add the complexity of the environment (or plant) under control to the test platform Test and verify the embedded system or control unit by using a real-time target environment	Deploy Algorithm Model for Real-Time Rapid Prototyping Deploy Environment Model for Real-Time Hardware-In-the-Loop (HIL) Simulation Deploy Generated Standalone Executable Programs To Target Hardware Deploy Generated Component Software to Application Target Platforms
Generate source code for HIL testing	Code Generation Code Generation Deploy Environment Model for Real-Time Hardware-In-the-Loop (HIL) Simulation
Conduct hard real-time HIL testing using PCs	Simulink Real-Time	Create and Run Real-Time Application from Simulink Model (Simulink Real-Time) Real-Time Simulation and Testing (Simulink Real-Time)
Tune ECU properly for its intended use	Data Exchange Interfaces Data Exchange Interfaces	`rtwdemo_capi` `rtwdemo_asap2`
Generate ASAP2 data files	Export ASAP2 File for Data Measurement and Calibration	`rtwdemo_asap2`
Generate C API data interface files	Exchange Data Between Generated and External Code Using C API	`rtwdemo_capi`

Documentation