HDL Code Generation

Generate HDL code from MATLAB® and Simulink®

To implement a DSP design on FPGAs or ASICs, you can use either HDL Coder™ or Filter Design HDL Coder™. Both products generate synthesizable and portable VHDL® and Verilog® code, and also generate VHDL and Verilog test benches for quickly simulating, testing, and verifying the generated code.

  • HDL Coder — Generate code from Simulink or MATLAB designs. This support includes filters, math and signal operations, and other algorithms optimized for resource use and performance, such as the FFT HDL Optimized, IFFT HDL Optimized, and NCO HDL Optimized blocks. For a basic example of how to generate HDL code using HDL Coder, see Programmable FIR Filter for FPGA.

  • Filter Design HDL Coder — Generate code from MATLAB filter designs. You can access code and test bench generation features using the Generate HDL user interface, or by using command-line options. These features are also integrated with the Filter Designer app. For an example of how to generate HDL code using Filter Design HDL Coder, see HDL Butterworth Filter (Filter Design HDL Coder).

To debug your designs in Simulink or MATLAB, use the Logic Analyzer waveform viewer.

Simulink Visualization Tool

Logic AnalyzerVisualize, measure, and analyze transitions and states over time

Functions

generatehdlGenerate HDL code for quantized DSP filter (requires Filter Design HDL Coder)

Topics

Find Blocks That Support HDL Code Generation

Filter for blocks that support HDL code generation in the Simulink library browser and in documentation.

Generate HDL Code for Filter System Objects (Filter Design HDL Coder)

Learn about the specifics of HDL code generation from filter System objects.

HDL Filter Architectures

Select HDL code generation parameters to control speed vs. area tradeoffs in filter architectures.

Subsystem Optimizations for Filters

Select resource sharing and pipeline optimization options.

High Throughput HDL Algorithms

Choose a block that supports frame-based input for HDL code generation.

Visualizing Multiple Signals Using Logic Analyzer

Visualize multiple signals of a programmable FIR filter by using a logic analyzer.

Featured Examples

Programmable FIR Filter for FPGA

Programmable FIR Filter for FPGA

Implement a programmable FIR filter for hardware. You can program the filter to a desired response by loading the coefficients into internal registers using the host interface.

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Multichannel FIR Filter for FPGA

Multichannel FIR Filter for FPGA

Implement a discrete FIR filter with multiple input data streams for hardware.

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High Throughput Channelizer for FPGA

High Throughput Channelizer for FPGA

Implement a high throughput (Gigasamples per second, GSPS) channelizer for hardware by using a polyphase filter bank.

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Implement FFT for FPGA Using FFT HDL Optimized Block

Implement FFT for FPGA Using FFT HDL Optimized Block

Use the FFT HDL Optimized block to implement a FFT for hardware.

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Implementing the Filter Chain of a Digital Down-Converter in HDL

Implementing the Filter Chain of a Digital Down-Converter in HDL

Use the DSP System Toolbox™ and Fixed-Point Designer™ to design a three-stage, multirate, fixed-point filter that implements the filter chain of a Digital Down-Converter (DDC) designed to meet the Global System for Mobile (GSM) specification.

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Optimized Fixed-Point FIR Filters

Optimized Fixed-Point FIR Filters

Optimize fixed-point FIR filters. The optimization can refer to the characteristics of the filter response such as the stopband attenuation or the number of bits required to achieve a particular specification. This functionality is particularly useful for users targeting hardware that have a number of configurable coefficients of a specific wordlength and/or in cases typically found on ASICs and FPGAs where there is a large design space to explore. A hardware designer can usually trade off more coefficients for less bits or vice-versa to optimize for different ASICs or FPGAs.

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HDL Implementation of a Digital Down-Converter for LTE

HDL Implementation of a Digital Down-Converter for LTE

Design a digital down-converter (DDC) for radio communication applications such as LTE, and generate HDL code with HDL Coder™.

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DSP System Toolbox Documentation

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