Convolutional Encoder

Create convolutional code from binary data

Library

Convolutional sublibrary of Error Detection and Correction

Description

The Convolutional Encoder block encodes a sequence of binary input vectors to produce a sequence of binary output vectors. This block can process multiple symbols at a time.

This block can accept inputs that vary in length during simulation. For more information about variable-size signals, see Variable-Size Signal Basics (Simulink).

Input and Output Sizes

If the encoder takes k input bit streams (that is, it can receive 2^k possible input symbols), the block input vector length is L*k for some positive integer L. Similarly, if the encoder produces n output bit streams (that is, it can produce 2ⁿ possible output symbols), the block output vector length is L*n.

This block accepts a column vector input signal with any positive integer for L. For variable-size inputs, the L can vary during simulation. The operation of the block is governed by the Operation mode parameter.

For both its inputs and outputs for the data ports, the block supports double, single, boolean, int8, uint8, int16, uint16, int32, uint32, and ufix1. The port data types are inherited from the signals that drive the block. The input reset port supports double and boolean typed signals.

Specifying the Encoder

To define the convolutional encoder, use the Trellis structure parameter. This parameter is a MATLAB^® structure whose format is described in Trellis Description of a Convolutional Code. You can use this parameter field in two ways:

If you have a variable in the MATLAB workspace that contains the trellis structure, enter its name in the Trellis structure parameter. This way is preferable because it causes Simulink^® to spend less time updating the diagram at the beginning of each simulation, compared to the usage described next.
If you want to specify the encoder using its constraint length, generator polynomials, and possibly feedback connection polynomials, use a poly2trellis command in the Trellis structure parameter. For example, to use an encoder with a constraint length of 7, code generator polynomials of 171 and 133 (in octal numbers), and a feedback connection of 171 (in octal), set the Trellis structure parameter to
```
poly2trellis(7,[171 133],171)
```

The encoder registers begin in the all-zeros state. Set the Operation mode parameter to Reset on nonzero input via port to reset all encoder registers to the all-zeros state during the simulation. This selection opens a second input port, labeled Rst, which accepts a scalar-valued input signal. When the input signal is nonzero, the block resets before processing the data at the first input port. To reset the block after it processes the data at the first input port, select Delay reset action to next time step.

Parameters

Trellis structure

MATLAB structure that contains the trellis description of the convolutional encoder.

Operation mode

In Continuous mode, the block retains the encoder states at the end of each input, for use with the next frame.

In Truncated (reset every frame) mode, the block treats each input independently. The encoder states are reset to all-zeros state at the start of each input.

Note

When this block outputs sequences that vary in length during simulation and you set the Operation mode to Truncated (reset every frame) or Terminate trellis by appending bits, the block's state resets at every input time step.

In Terminate trellis by appending bits mode, the block treats each input independently. For each input frame, extra bits are used to set the encoder states to all-zeros state at the end of the frame. The output length is given by $y = n \cdot (x + s) / k$ , where x is the number of input bits, and $s = constraint length - 1$ (or, in the case of multiple constraint lengths, s =sum(ConstraintLength(i)-1)).

Note

This block works for cases $k \geq 1$ , where it has the same values for constraint lengths in each input stream (e.g., constraint lengths of [2 2] or [7 7] will work, but [5 4] will not).

In Reset on nonzero input via port mode, the block has an additional input port, labeled Rst. When the Rst input is nonzero, the encoder resets to the all-zeros state.

Delay reset action to next time step

When you select Delay reset action to next time step, the Convolutional Encoder block resets after computing the encoded data. This check box only appears when you set the Operation mode parameter to Reset on nonzero input via port.

The delay in the reset action allows the block to support HDL code generation. In order to generate HDL code, you must have an HDL Coder™ license.

Output final state

When you select Output final state, the second output port signal specifies the output state for the block. The output signal is a scalar, integer value. You can select Output final state for all operation modes except Terminate trellis by appending bits .

Specify initial state via input port

When you select Specify initial state via input port the second input port signal specifies the starting state for every frame in the block. The input signal must be a scalar, integer value. Specify initial state via input port appears only in Truncated operation mode.

Puncture code

Selecting this option opens the field Puncture vector.

Puncture vector

Vector used to puncture the encoded data. The puncture vector is a pattern of 1s and 0s where the 0s indicate the punctured bits. This field appears when you select Punctured code.

Puncture Pattern Examples

For some commonly used puncture patterns for specific rates and polynomials, see the last three references listed on this page.

References

[1] Clark, George C. Jr. and J. Bibb Cain, Error-Correction Coding for Digital Communications, New York, Plenum Press, 1981.

[2] Gitlin, Richard D., Jeremiah F. Hayes, and Stephen B. Weinstein, Data Communications Principles, New York, Plenum, 1992.

[3] Yasuda, Y., et. al., “High rate punctured convolutional codes for soft decision Viterbi decoding,” IEEE Transactions on Communications, Vol. COM-32, No. 3, pp 315–319, March 1984.

[4] Haccoun, D., and Begin, G., “High-rate punctured convolutional codes for Viterbi and Sequential decoding,” IEEE Transactions on Communications, Vol. 37, No. 11, pp 1113–1125, Nov. 1989.

[5] Begin, G., et.al., “Further results on high-rate punctured convolutional codes for Viterbi and sequential decoding,” IEEE Transactions on Communications, Vol. 38, No. 11, pp 1922–1928, Nov. 1990.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Restrictions

Input data requirements:
- Must be sample-based,
- Must have a boolean or ufix1 data type.
HDL Coder supports only the following coding rates:
- ½ to 1/7
- 2/3
The coder supports only constraint lengths for 3 to 9.
Specify Trellis structure by the poly2trellis function.
The coder supports the following Operation mode settings:
- Continuous
- Reset on nonzero input via port
  If you select this mode, you must select the Delay reset action to next time step option. When you select this option, the Convolutional Encoder block finishes its current computation before executing a reset.
You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).

Introduced before R2006a

Documentation

Convolutional Encoder

Library

Description

Input and Output Sizes

Specifying the Encoder

Parameters

Puncture Pattern Examples

See Also

References

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Communications Toolbox Documentation

Support

Documentation

Convolutional Encoder

Library

Description

Input and Output Sizes

Specifying the Encoder

Parameters

Puncture Pattern Examples

See Also

References

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Communications Toolbox Documentation

Support

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.