BPSK Modulator Baseband

Modulate signal by using BPSK method

Library:
Communications Toolbox / Modulation / Digital Baseband Modulation / PM
Communications Toolbox HDL Support / Modulation / PM

Description

The BPSK Modulator Baseband block modulates a signal by using the binary phase shift keying (BPSK) method. The output is a baseband representation of the modulated signal.

The input signal must be a discrete-time binary-valued signal. If the input bit is 0 or 1, then the modulated symbol is exp(jθ) or -exp(jθ), respectively, where θ represents the Phase offset (rad) parameter.

Ports

Input

expand all

`Port_1` — Input data
scalar | vector

Input signal, specified as a scalar or vector.

If you specify a scalar, it must be an integer from 0 to M – 1, where M is the modulation order.
If you specify a vector, the elements must be either integers from 0 to M-1 or binary values. If you specify a binary vector, the number of elements must be an integer multiple of the number of bits per symbol. The number of bits per symbol is equal to log₂(M).

Output

expand all

`Port_1` — BPSK-modulated baseband signal
scalar | vector

BPSK-modulated baseband signal, returned as a complex scalar or vector of complex values.

Data Types: single | double | fixed point
Complex Number Support: Yes

Parameters

expand all

`Phase offset (rad)` — Phase of zeroth point
`0` (default) | finite real-valued scalar

Specify a finite real-valued scalar for the phase of the zeroth point of the constellation in radians.

Example: pi/4

`Output data type` — Output data type
`double` (default) | `single` | `Inherit via back propagation` | `fixdt(1,16)` | `fixdt(1,16,0)` | `<data type expression>`

Data type of output,. Set this parameter to one of the fixed point options or <data type expression> to enable parameters in which you specify additional details. Set this parameter to Inherit via back propagation, to match the output data type and scaling to the following block in the model.

Model Examples

Cyclic Redundancy Check of Noisy BPSK Data Frames in Simulink

Use a CRC code to detect frame errors in a noisy BPSK signal.

Frame Synchronization Using Barker Code Preamble

Use a length 13 Barker code frame preamble for frame synchronization of data bits.

Block Characteristics

Data Types	`Boolean` \| `double` \| `fixed point^[a]^[b]` \| `integer` \| `single`
Multidimensional Signals	`no`
Variable-Size Signals	`yes`
^[a] ufix(ceil(log2(M))) only at the input for M-ary modulation. ^[b] Fixed-point outputs must be signed.

Tips

The BPSK Modulator Baseband block provides the capability to visualize a signal constellation from the block mask. This constellation visualization feature allows you to visualize a signal constellation for the specified block parameters. For more information, see the Constellation Visualization section of the Communications Toolbox™ User's Guide.

Algorithms

Phase modulation is a linear baseband modulation technique in which the message modulates the phase of a constant amplitude signal. Binary Phase Shift Keying (BPSK) is a two phase modulation scheme, where the 0’s and 1’s in a binary message are represented by two different phase states in the carrier signal

$s_{n} (t) = \sqrt{\frac{2 E_{b}}{T_{b}}} \cos (2 π f_{c} t + π (1 - n)); n \in {0, 1},$

where:

E_b is the energy per bit.
T_b is the bit duration.
f_c is the carrier frequency.

In MATLAB^®, the baseband representation of a BPSK signal is

$s_{n} (t) = \cos (π n); n \in {0, 1} .$

The BPSK signal has two phases: 0 and π.

The probability of a bit error in an AWGN channel is

$P_{b} = Q (\sqrt{\frac{2 E_{b}}{N_{0}}}),$

where N₀ is the noise power spectral density.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Documentation

BPSK Modulator Baseband

Description

Ports

Input

`Port_1` — Input data
scalar | vector

Output

`Port_1` — BPSK-modulated baseband signal
scalar | vector

Parameters

`Phase offset (rad)` — Phase of zeroth point
`0` (default) | finite real-valued scalar

`Output data type` — Output data type
`double` (default) | `single` | `Inherit via back propagation` | `fixdt(1,16)` | `fixdt(1,16,0)` | `<data type expression>`

Model Examples

Cyclic Redundancy Check of Noisy BPSK Data Frames in Simulink

Frame Synchronization Using Barker Code Preamble

Block Characteristics

Tips

Algorithms

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Objects

Blocks

Communications Toolbox Documentation

Support

Documentation

BPSK Modulator Baseband

Description

Ports

Input

Port_1 — Input data scalar | vector

Output

Port_1 — BPSK-modulated baseband signal scalar | vector

Parameters

Phase offset (rad) — Phase of zeroth point 0 (default) | finite real-valued scalar

Output data type — Output data type double (default) | single | Inherit via back propagation | fixdt(1,16) | fixdt(1,16,0) | <data type expression>

Model Examples

Cyclic Redundancy Check of Noisy BPSK Data Frames in Simulink

Frame Synchronization Using Barker Code Preamble

Block Characteristics

Tips

Algorithms

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Objects

Blocks

Communications Toolbox Documentation

Support

`Port_1` — Input data
scalar | vector

`Port_1` — BPSK-modulated baseband signal
scalar | vector

`Phase offset (rad)` — Phase of zeroth point
`0` (default) | finite real-valued scalar

`Output data type` — Output data type
`double` (default) | `single` | `Inherit via back propagation` | `fixdt(1,16)` | `fixdt(1,16,0)` | `<data type expression>`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.