BPSK Demodulator Baseband

Demodulate BPSK-modulated data

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  • Library:

  • Communications Toolbox / Modulation / Digital Baseband Modulation / PM

    Communications Toolbox HDL Support / Modulation / PM

  • BPSK Demodulator Baseband block

Description

The BPSK Demodulator Baseband block demodulates a signal that was modulated using the binary phase shift keying method. The input is a baseband representation of the modulated signal. This block accepts a scalar or column vector input signal. The input signal must be a discrete-time complex signal. The block maps the points exp(jθ) and -exp(jθ) to 0 and 1, respectively, where θ is the Phase offset parameter.

Ports

Input

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BPSK-modulated signal, specified as a scalar, vector, or matrix. When this input is a matrix, each column is treated as an independent channel.

Data Types: double | single | fixed point
Complex Number Support: Yes

Output

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Demodulated signal, returned as a scalar or vector. If the output is a scalar, the value is an integer. If the output is a vector, it is an integer-valued or binary-valued vector.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean

Parameters

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When you set the Decision type parameter to Hard decision, you can set this parameter to Inherit via internal rule, Smallest unsigned integer, double, single, int8, uint8, int16, uint16, int32, uint32, or boolean.

When you set this parameter to Inherit via internal rule, the block inherits the output data type from the input port. If the input is a floating-point type (single or double) the output data type is the same as the input data type. If the input data type is fixed-point, the output data type will work as if this parameter is set to Smallest unsigned integer.

When you set this parameter to Smallest unsigned integer, the block selects the output data type based on the settings used in the Hardware Implementation pane of the Configuration Parameters dialog box of the model. If you select ASIC/FPGA is selected in the Hardware Implementation pane, the output data type is the ideal minimum one-bit size, that is., ufix(1). For all other selections, the output data type is an unsigned integer with the smallest available word length large enough to fit one bit. This value usually corresponds to the size of a character (for example, uint8).

Derotate factor, specified as Same word length as input or Specify word length. This parameter applies only when the input is fixed-point and the Phase offset (rad) parameter is not a multiple of π/2.

Decision type used during demodulation, specified as Hard decision, Log-likelihood ratio or Approximate log-likelihood ratio. The output values when you select Log-likelihood ratio and Approximate log-likelihood ratio are of the same data type as the input values. For algorithm details, see Exact LLR Algorithm and Approximate LLR Algorithm in the Communications Toolbox™ User's Guide for algorithm details.

Noise variance source, specified as Dialog or Port.

Select Dialog to specify the noise variance using the Noise variance parameter. Select Portto enable the port to input the noise variance.

This parameter specifies the noise variance in the input signal. This parameter is tunable in normal mode, accelerator mode and rapid accelerator mode.

If you use the Simulink® Coder™ rapid simulation (RSIM) target to build an RSIM executable, then you can tune the parameter without recompiling the model. This is useful for Monte Carlo simulations, in which you run the simulation multiple times (perhaps on multiple computers) with different amounts of noise.

The LLR algorithm involves computing exponentials of very large or very small numbers using finite precision arithmetic and yields:

  • Inf to -Inf if Noise variance is very high

  • NaN if Noise variance and the signal power are both very small

In such cases, use approximate LLR, as its algorithm does not involve computing exponentials.

Dependencies

To enable this parameter, set the Noise variance source parameter to Dialog.

Phase of the zeroth point, specified as a real-valued scalar. Units are in radians.

Example: pi/4

Datatype of output, specified as one of these options.

  • Inherit via internal rule

  • Smallest unsigned integer

  • double

  • single

  • int8

  • uint8

  • int16

  • uint16

  • int32

  • uint32

  • boolean

When you set the Decision type parameter to

  • Hard decision, you can set this parameter to Inherit via internal rule, Smallest unsigned integer, double, single, int8, uint8, int16, uint16, int32, uint32, or boolean

  • Inherit via internal rule (default), the block inherits the output data type from the input port. If the input is a floating-point type (single or double), the output data type is the same as the input data type. If the input data type is fixed-point, the output data type works as if you set this parameter to Smallest unsigned integer.

  • Smallest unsigned integer, the block selects the output data type based on the settings used in the Hardware Implementation pane of the Configuration Parameters dialog box of the model. If you select ASIC/FPGA in the Hardware Implementation pane, the output data type is the ideal minimum one-bit size, that is, ufix(1). For all other selections, the output data type is an unsigned integer with the smallest available word length large enough to fit one bit, usually corresponding to the size of a character (for example, uint8).

  • Log-likelihood ratio or Approximate log-likelihood ratio, the block inherits the output data type from the input (for example, if the input is of data type double, the output is also of data type double).

Model Examples

Cyclic Redundancy Check of Noisy BPSK Data Frames in Simulink

Cyclic Redundancy Check of Noisy BPSK Data Frames in Simulink

Use a CRC code to detect frame errors in a noisy BPSK signal.

Frame Synchronization Using Barker Code Preamble

Frame Synchronization Using Barker Code Preamble

Use a length 13 Barker code frame preamble for frame synchronization of data bits.

Block Characteristics

Data Types

Boolean | double | fixed point[a][b] | integer | single

Multidimensional Signals

no

Variable-Size Signals

yes

[a] Fixed-point inputs must be signed.

[b] ufix(1) only at the output when ASIC/FPGA is selected in the Hardware Implementation Pane.

Algorithms

Hard-Decision BPSK Demodulator Signal Diagram for Trivial Phase Offset (multiple of π/2)

Hard-Decision BPSK Demodulator Floating-Point Signal Diagram for Nontrivial Phase Offset

Hard-Decision BPSK Demodulator Fixed-Point Signal Diagram for Nontrivial Phase Offset

For more details about the exact LLR and approximate LLR cases (soft-decision), see Exact LLR Algorithm and Approximate LLR Algorithm in the Communications Toolbox User's Guide.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

See Also

Blocks

Introduced before R2006a

Communications Toolbox Documentation

Support