Adaptive pipelining

This parameter resides in the HDL Code Generation > Optimization > Pipelining tab of the Configuration Parameters dialog box. Use this parameter to insert pipeline registers to the blocks in your design, reduce the area usage, and maximize the achievable clock frequency on the target FPGA device.

Settings

Default: On

On: Insert adaptive pipeline registers in your design. For HDL Coder™ to insert adaptive pipelines, you must specify the synthesis tool.
Off: Do not insert adaptive pipeline registers.

Dependency

When you specify this parameter, in the HDL Code Generation > Targetpane:

Specify the Synthesis Tool. If your design has multipliers, specify the Synthesis Tool and the Target Frequency (MHz) for adaptive pipeline insertion.
In the General tab, make sure that the Clock-rate pipelining check box is selected to insert pipeline registers at the faster clock rate.
In the General tab, make sure that the Balance delays check box is selected.
In the Resource Sharing tab, enable Adders, and specify the SharingFactor on the DUT Subsystem to share resources and insert adaptive pipelines, which saves area and improves timing.

Command-Line Information

Property: AdaptivePipelining

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can use the ClockRatePipelineOutputPorts setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'ClockRatePipelineOutputPorts','on')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','ClockRatePipelineOutputPorts','on')
makehdl('sfir_fixed/symmetric_fir')
```

Documentation