GenerateSVDPITestbench

Generate SystemVerilog DPI test bench

Settings

'ModelSim' (default)

Generate SystemVerilog DPI test bench, and build-and-run scripts, for the Mentor Graphics® ModelSim® simulator.

'Incisive'

Generate SystemVerilog DPI test bench, and build-and-run scripts, for the Cadence Incisive® simulator.

'VCS' (default)

Generate SystemVerilog DPI test bench, and build-and-run scripts, for the Synopsys® VCS® simulator.

'Vivado'

Generate SystemVerilog DPI test bench, and build-and-run scripts, for the Xilinx® Vivado® simulator.

When you set this property, the coder generates a direct programming interface (DPI) component for your entire Simulink® model, including your DUT and data sources. Your entire model must support C code generation with Simulink Coder™. The coder generates a SystemVerilog test bench that compares the output of the DPI component with the output of the HDL implementation of your DUT. The coder also builds shared libraries and generates a simulation script for the simulator you select.

Consider using this option if the default HDL test bench takes a long time to generate or simulate. Generation of a DPI test bench is sometimes faster than the default version because it does not run a full Simulink simulation to create the test bench data. Simulation of a DPI test bench with a large data set is faster than the default version because it does not store the input or expected data in a separate file.

To use this feature, you must have HDL Verifier™ and Simulink Coder licenses. To run the SystemVerilog testbench with generated VHDL code, you must have a mixed-language simulation license for your HDL simulator.

Limitations

This test bench is not supported when you generate HDL code for the top-level Simulink model. Your DUT subsystem must meet the following conditions:

  • Input and output data types of the DUT cannot be larger than 64 bits.

  • Input and output ports of the DUT cannot use enumerated data types.

  • Input and output ports cannot be single-precision or double-precision data types.

  • The DUT cannot have multiple clocks. You must set the Clock inputs code generation option to Single.

  • Use trigger signal as clock must not be selected.

  • If the DUT uses vector ports, you must use Scalarize vector ports to flatten the interface.

Set or View This Property

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

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