Documentation

Clocking and Multirate Design

Clock generation, HDL code generation guidelines for multirate models

Properties

HoldInputDataBetweenSamples Specify how long subrate signal values are held in valid state

Simulink Configuration Parameters

Timing Controller and Clocks

Timing Controller Settings

Clock Settings and Timing Controller Postfix

Oversampling factor

Use trigger signal as clock

Reset and Clock Enable

Clock Enable Settings

RTL Description Rules for clock enables and resets

Minimize Clock Enables and Reset Signals

Clock Enable output port

Test Bench Stimulus

Clock Input Signals

Test Bench Stimulus and Output

Examples and How To

Generate a Global Oversampling Clock

In many designs, the DUT is not self-contained.

Using Triggered Subsystems for HDL Code Generation

How to use Triggered Subsystems, Trigger As Clock property, and generate HDL code.

Generate Reset for Timing Controller

How to generate reset for timing controller

Concepts

Code Generation from Multirate Models

Overview of HDL code generation for single-clock, single-tasking multirate models

Multirate Model Requirements for HDL Code Generation

Guidelines for setting up multirate models and blocks for HDL code generation.

Timing Controller for Multirate Models

A timing controller entity generates the required rates from a single master clock, using one or more counters to create multiple clock enables.

Featured Examples

Using Multiple Clocks in HDL Coder™

Using Multiple Clocks in HDL Coder™

Instantiate multiple top-level synchronous clock input ports in HDL Coder.

HDL Coder Documentation

Support