NR LDPC Decoder

Decode LDPC code using layered belief propagation with min-sum or normalized min-sum approximation algorithm

Library:
Wireless HDL Toolbox / Error Detection and Correction

Description

The NR LPDC Decoder block implements a low-density parity-check (LDPC) decoder with hardware-friendly control signals. The block accepts punctured log-likelihood ratio (LLR) values, a stream of control signals, a base graph number, and lifting sizes. The block outputs decoded bits, a stream of control signals, lifting sizes, and a signal that indicates when the block is ready to accept new inputs.

This block provides an option to implement layered belief propagation with either the normalized min-sum approximation algorithm or the min-sum approximation algorithm. This implementation matches that of the function nrLDPCDecode (5G Toolbox). You can use this block for channel coding of downlink and uplink shared channels and paging channel according to 5G new radio (NR) standard TS 38.212 [1].

The block supports scalar and vector inputs. The block provides an architecture suitable for HDL code generation and hardware deployment. For more information, see Algorithms.

Ports

Input

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`data` — Input LLR values
scalar | vector

Input log-likelihood ratio (LLR) values, specified as a scalar or a column vector of size 64.

The data type of this input must be a signed fixed-point data type with a word length from 4 to 16 bits. For more information on how to specify vector input data, see Specifying Vector Input.

Data Types: int8 | int16 | fixed point

`ctrl` — Control signals accompanying sample stream
`samplecontrol` bus

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

start — Indicates the start of the input frame
end — Indicates the end of the input frame
valid — Indicates that the data on the input data port is valid

For more detail, see Sample Control Bus.

Data Types: bus

`bgn` — Base graph number
scalar

Base graph number, specified as a scalar. When this value is 0, the block applies bgn 1. When this value is 1, the block applies bgn 2. For more information about bgn 1 and bgn 2, see section 5.3.2, of TS 38.212 [1].

Data Types: Boolean

`liftingSize` — Input lifting size
scalar

Input lifting size, specified as a scalar.

For an invalid liftingSize value, the block discards the current frame and waits for the new frame.

For more information about the supported lifting size values, see section 5.3.2, of TS 38.212 [1].

Data Types: uint16

`iter` — Number of iterations
scalar

Number of iterations, specified as a integer scalar in the range from 1 to 63.

If you specify iter as a value greater than 63, the block automatically sets the iter value to 8 and performs the decoding operation.

Dependencies

To enable this port, set the Source for number of iterations parameter to Input port.

Data Types: uint8

Output

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`data` — Decoded output data bits
scalar | vector

Decoded output data bits, returned as a scalar or a column vector of size 64.

The block outputs data bits in a similar format as the input LLR values. Extract these output data bits in a similar format for further processing.

Data Types: Boolean

`ctrl` — Control signals accompanying sample stream
`samplecontrol` bus

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

start — Indicates the start of the output frame
end — Indicates the end of the output frame
valid — Indicates that the data on the output data port is valid

For more detail, see Sample Control Bus.

Data Types: bus

`liftingSize` — Output lifting size
scalar

Output lifting size, returned as a scalar.

Data Types: uint16

`nextFrame` — Ready for new inputs
scalar

The block sets this signal to 1 when the block is ready to accept the start of the next frame. If the block receives an input start signal while nextFrame is 0, the block discards the frame in progress and begins processing the new data.

For more information, see Using the nextFrame Output Signal.

Data Types: Boolean

Parameters

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`Algorithm` — Type of algorithm
`Min-sum` (default) | `Normalized min-sum`

Select the type of algorithm. For more information, see Algorithm (5G Toolbox).

`Scaling factor` — Scaling factor
`0.75` (default) | values in the range from 0.5 to 1, incremented by 0.0625

Specify the scaling factor.

Dependencies

To enable this parameter, set the Algorithm parameter to Normalized min-sum.

`Source for number of iterations` — Source selection for number of iterations
`Property` (default) | `Input port`

Select the source for specifying the number of iterations.

You can set number of iterations with an input port or by specifying a value for the parameter.

Select Property to enable the Source for number of iterations parameter.
Select Input port to enable the iter port.

`Number of iterations` — Number of iterations
`8` (default) | integer in the range from 1 to 63

Specify the number of iterations.

Dependencies

To enable this parameter, set the Source for number of iterations parameter to Property.

Model Examples

LDPC Encode and Decode of Streaming Data

Simulate the NR LDPC Encoder and NR LDPC Decoder Simulink® blocks and compare the hardware-optimized results with the results from the 5G Toolbox™ functions. These blocks support scalar and vector inputs. The NR LDPC Decoder block enables you to select either Min-sum or Normalized min-sum algorithm for decoding operation.

More About

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Specifying Vector Input

Vector input data for the block must be specified as a column vector of size 64. You must provide inputs as an integer number of ceil(liftingSize/64) clock cycles.

The total number of clock cycles that the block requires to receive a frame of LLR values for decoding is equal to n x ceil(liftingSize/64), where n is the number of columns in the parity check matrix. n depends on the base graph number, specified by the bgn input port. When the bgn port value is 0, the block sets n to 66. When the bgn port value is 1, the block sets n to 50.

These sections show how the block accepts input LLR values based on the liftingSize and bgn port values.

liftingSize input value is less than 64 and bgn value is 0

For a liftingSize input value of 2, the block accepts the first two LLR input bits in each clock cycle and ignores the remaining 62 elements in that clock cycle. The total number of clock cycles the block requires to receive a frame of LLR values is 66.

The L_n elements represent LLR bits, and the X elements represent ignored values.

Input LLR Values	Number of Clock Cycles
Input LLR Values	1 Clock Cycle	2 Clock Cycles	3 Clock Cycles	4 Clock Cycles	...	66 Clock Cycles
`data[0]`	L₀	L₂	L₄	L₆	...	L₁₃₀
`data[1]`	L₁	L₃	L₅	L₇	...	L₁₃₁
...	X	X	X	X	X	X
`data[63]`	X	X	X	X	X	X

liftingSize input value is greater than 64 and bgn value is 0

For a liftingSize input value of 104, the block accepts 104 LLR values in two clock cycles: 64 LLRs in the first clock cycle and 40 LLRs in the second clock cycle. The block ignores the remaining 24 elements in the second clock cycle. The total number of clock cycles the block requires to receive input LLR values is 132.

The L_n elements represent LLR bits, and the X elements represent ignored values.

Input LLR Values	Number of Clock Cycles
Input LLR Values	1 Clock Cycle	2 Clock Cycles	3 Clock Cycles	4 Clock Cycles	...	...	131 Clock Cycles	132 Clock Cycles
`data[0]`	L₀	L₆₄	L₁₀₄	L₁₆₈	...	...	L₆₇₆₀	L₆₈₂₄
`data[1]`	L₁	L₆₅	L₁₀₅	L₁₆₉	...	...	L₆₇₆₁	L₆₈₂₅
	...	...	...		...	...	...	...
...	...	L₁₀₃	...	L₂₀₇	...	...	...	L₆₈₆₃
...	...	X	...	X	...	...	...	X
`data[63]`	L₆₃	X	L₁₆₇	X	...	...	L₆₈₂₃	X

Algorithms

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This figure shows the architecture block diagram of the NR LDPC Decoder block. The Functional Processing Unit block calculates the variable node (VN) messages and check node (CN) messages based on the layered belief propagation with either the normalized min-sum approximation algorithm or the min-sum approximation algorithm. For more information, see Algorithm (5G Toolbox).

The implementation of the block matches the performance of the function nrLDPCDecode (5G Toolbox). This plot shows the performance of the block for a 4-bit LLR input when the Algorithm parameter is set to Min-sum.

This plot shows the performance of the block for a 4-bit LLR input when the Algorithm parameter is set to Normalized min-sum.

Latency

The latency of the block varies based on the values of the bgn and liftingSize input ports, and the specified number of iterations. Because the latency varies, use the nextFrame control signal to determine when the block is ready for a new input frame.

Scalar Input

The latency of the block is equal to r x (t + (m x 8) x ceil(liftingSize/64) + t + m x ( 7 – ceil(liftingSize/64))) + (n x liftingSize) + 18. In this calculation, r is the number of iterations, n is the number of columns in the parity check matrix, t is twice the total number of non —1 elements in the parity check matrix, and m is the number of rows in the parity check matrix.

This figure shows a sample output of the NR LDPC Decoder block with latency. In this case, the bgn, liftingSize input port values are set to 0 and 128, respectively and the Number of iterations parameter is set to 8. The latency of the block is 31,362 clock cycles.

Vector Input

For vector inputs, the latency of the block is equal to r x (t + (m x 9) + n x (ceil(liftingSize/64))) + 18. In this calculation, r is the number of iterations, n is the number of columns in the parity check matrix, t is twice the total number of non —1 elements in the parity check matrix, and m is the number of rows in the parity check matrix.

This figure shows a sample output of the NR LDPC Decoder block with latency. In this case, the bgn, liftingSize input port values are set to 0 and 384, respectively and the Number of iterations parameter is set to 8. The latency of the block is 8,782 clock cycles.

Performance

The performance of the synthesized HDL code varies with your target and synthesis options. It also varies based on the type of algorithm and the word length of the input LLR values.

This table shows the resource and performance data synthesis results of the block when the Algorithm parameter is set to Min-sum, the Number of iterations parameter is set to 8, and the input LLR values are of data type fixdt(1,4,0). The generated HDL is targeted to the Xilinx^® Zynq^®Ultrascale+™ RFSoC evaluation board.

Input Data	Slice LUTs	Slice Registers	Block RAMs	Maximum Frequency in MHz
Scalar	53095	64305	115	291
Vector	69335	75296	147.5	293

References

[1] 3GPP TS 38.212. “NR; Multiplexing and Channel Coding.” 3rd Generation Partnership Project; Technical Specification Group Radio Access Network.

[2] Gallager, R. “Low-Density Parity-Check Codes.” IEEE Transactions on Information Theory 8, no. 1 (January 1962): 21–28. www.doi.org/10.1109/TIT.1962.1057683.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Restrictions

You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).

Documentation

NR LDPC Decoder

Description

Ports

Input

`data` — Input LLR values
scalar | vector

`ctrl` — Control signals accompanying sample stream
`samplecontrol` bus

`bgn` — Base graph number
scalar

`liftingSize` — Input lifting size
scalar

`iter` — Number of iterations
scalar

Dependencies

Output

`data` — Decoded output data bits
scalar | vector

`ctrl` — Control signals accompanying sample stream
`samplecontrol` bus

`liftingSize` — Output lifting size
scalar

`nextFrame` — Ready for new inputs
scalar

Parameters

`Algorithm` — Type of algorithm
`Min-sum` (default) | `Normalized min-sum`

`Scaling factor` — Scaling factor
`0.75` (default) | values in the range from 0.5 to 1, incremented by 0.0625

Dependencies

`Source for number of iterations` — Source selection for number of iterations
`Property` (default) | `Input port`

`Number of iterations` — Number of iterations
`8` (default) | integer in the range from 1 to 63

Dependencies

Model Examples

LDPC Encode and Decode of Streaming Data

More About

Specifying Vector Input

Algorithms

Latency

Performance

References

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Blocks

Functions

Wireless HDL Toolbox Documentation

Support

Documentation

NR LDPC Decoder

Description

Ports

Input

data — Input LLR values scalar | vector

ctrl — Control signals accompanying sample stream samplecontrol bus

bgn — Base graph number scalar

liftingSize — Input lifting size scalar

iter — Number of iterations scalar

Dependencies

Output

data — Decoded output data bits scalar | vector

ctrl — Control signals accompanying sample stream samplecontrol bus

liftingSize — Output lifting size scalar

nextFrame — Ready for new inputs scalar

Parameters

Algorithm — Type of algorithm Min-sum (default) | Normalized min-sum

Scaling factor — Scaling factor 0.75 (default) | values in the range from 0.5 to 1, incremented by 0.0625

Dependencies

Source for number of iterations — Source selection for number of iterations Property (default) | Input port

Number of iterations — Number of iterations 8 (default) | integer in the range from 1 to 63

Dependencies

Model Examples

LDPC Encode and Decode of Streaming Data

More About

Specifying Vector Input

Algorithms

Latency

Performance

References

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Blocks

Functions

Wireless HDL Toolbox Documentation

Support

`data` — Input LLR values
scalar | vector

`ctrl` — Control signals accompanying sample stream
`samplecontrol` bus

`bgn` — Base graph number
scalar

`liftingSize` — Input lifting size
scalar

`iter` — Number of iterations
scalar

`data` — Decoded output data bits
scalar | vector

`ctrl` — Control signals accompanying sample stream
`samplecontrol` bus

`liftingSize` — Output lifting size
scalar

`nextFrame` — Ready for new inputs
scalar

`Algorithm` — Type of algorithm
`Min-sum` (default) | `Normalized min-sum`

`Scaling factor` — Scaling factor
`0.75` (default) | values in the range from 0.5 to 1, incremented by 0.0625

`Source for number of iterations` — Source selection for number of iterations
`Property` (default) | `Input port`

`Number of iterations` — Number of iterations
`8` (default) | integer in the range from 1 to 63

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.