The implementation of a digital predistorter (DPD) model that is optimized for HDL code generation and hardware implementation. The predistortion mechanism is executed in two stages. In the first stage, a set of DPD coefficients are estimated based on the input and output data of the power amplifier (PA). In the second stage, the input data of the PA is predistorted based on the estimated DPD coefficients and provided as new input to the PA. This example demonstrates a system-level simulation in which the DigitalPredistorter subsystem generates HDL code, while the DPD coefficient estimation generates C/C++ code. This example model supports only Normal and Accelerator simulation modes.