Documentation

VHDL: Package IEEE.std_logic_1164 must be included in each entity.

HDL Coder includes the package in each entity in the generated VHDL code.

No action required.

Verilog: A function description must assign return values to all possible states of the function.

HDL Coder does not generate functions for DUT.

No action required.

Verilog: Check using RTL parsing tool for error prevention.

HDL Coder generates VHDL and Verilog code with the correct syntax and complies with this rule.

No action required.

Verilog: Function statement should not be used for asynchronous reset line logic in an always construct for FF inference.

HDL Coder does not generate functions for DUT.

No action required.

VHDL: Use std_logic or std_logic_vector data types to describe ports of an entity.

At the inputs and outputs,HDL Coder uses std_logic or std_logic_vector to describe the ports.

No action required.

Verilog: Do not use nonblocking assignment, or input argument as input in function description.

The generated HDL code complies with this rule for Verilog.

No action required.

VHDL: Use range specification for integer types.

By default, HDL Coder specifies the range for integer types in the generated code.

No action required.

Verilog: Task constructs should not be used in the design.

HDL Coder does not use tasks or fork-join constructs in the Verilog code.

No action required.

VHDL: Do not use bit and bit vector data types in the design.

HDL Coder does not use bit or bit vector data types in the generated code.

No action required.

Verilog: Clock edges should not be used in a task description.

When generating Verilog code, HDL Coder does not use clock edges in a task description.

No action required.

VHDL: Specify range for std_logic_vector.

HDL Coder complies with this rule, because the generated VHDL code specifies the range that std_logic_vector uses.

No action required.

Verilog: Ensure that bitwidth of function arguments matches that of corresponding function inputs, and bitwidth of function return value matches that of assignment destination signal.

At module instantiation, HDL Coder enforces type matching, so that it complies with this rule.

No action required.

VHDL: Use only 'in', 'out', and 'inout' ports. Do not use buffer and linkage.

When generating VHDL code, HDL Coder specifies ‘IN’, ’OUT’, or ‘INOUT’ ports, and does not use buffer or linkage.

No action required.

Verilog: Use concatenation when assigning to multiple signals.

HDL Coder complies with this rule.

No action required.

VHDL: Port mode must be explicitly specified.

When generating VHDL code, HDL Coder specifies ‘IN’, ’OUT’, or ‘INOUT’ ports and does not use buffer or linkage.

No action required.

Verilog: In function description, do not assign global signals, and return value assignment must be the last statement.

HDL Coder generates Verilog code that complies with this rule.

No action required.

VHDL: Input port must not be described with initial value.

In the generated VHDL code, HDL Coder does not specify an initial value to the input port.

No action required.

Verilog: Bit-wise operators must be used instead of logical operators in multi-bit operations.

In the generated Verilog code, HDL Coder complies with this rule for multibit operators.

No action required.

Verilog: Reduction of a single-bit or large expression should not be performed.

By default, HDL Coder does not reduce a single-bit or a large expression. If your design performs bit-reduction operations, the resulting HDL code can perform reduction of a large expression.

Update your design so that there are no calls to bit reduction operations.

Verilog: Ensure that conditional expressions evaluate to a scalar.

HDL Coder complies with this rule.

No action required.

Verilog/VHDL: LSB of vectors/memory should be zero.

Your design contains vectors whose LSB has a nonzero value.

Update your design so that the generated code contains vectors or memory whose LSB value is zero.

Verilog/VHDL: Index variable width should not be too short.

HDL Coder enforces type matching and ensures that the index variable width is not too short.

No action required.

Verilog/VHDL: Do not use x and z for an array index.

In the generated code, HDL Coder does not use x or z for an array index.

No action required.

VHDL: Direct assignment must be used for aggregates.

HDL Coder directly assigns aggregates in the generated code without performing any intervening operations.

No action required.

VHDL: Constrained arrays should not be used as sub-program description.

In the generated code, HDL Coder does not use constrained arrays in subprogram description.

No action required.

VHDL: Specify range for return values in function description when return type is array.

In function description, when the return type is array, HDL Coder specifies the range for return values in function in the generated code.

No action required.

VHDL: In a sub-program description, use only OTHERS clause when specifying aggregates, not use or call a nested subprogram description, and not read Global signals.

HDL Coder complies with this rule.

No action required.

VHDL: A function must have a return statement, return a valid value in all possible states, and not have any other statement following the return statement.

HDL Coder complies with this rule.

No action required.

VHDL: Do not use user-defined attributes, or built-in attributes except range, length, left, right, high, low, reverse_range, and event.

By default, HDL Coder does not use user-defined attributes in the generated code. If you set HDL block properties, such as DSPStyle in your design, the generated code uses synthesis directives.

To fix this error, in your design, clear the HDL block property that you have set for using synthesis directives in the generated code.

VHDL: In a design, do not use block statements, objects of type record, shared variables, while-loop statements, procedures, or selected signal assignments.

If your design uses loop statements, HDL Coder generates this warning.

To avoid this warning, update your design so that there are no looping statements.

VHDL: In a design, do not use access types, alias declarations, bus and register signals, disconnect specifications, waveforms, and attributes that are defined in Synopsys library.

HDL Coder complies with this rule.

No action required.

Verilog/VHDL: Check latch creation from RTL lint checker and synthesis tools; Design should not have latches.

HDL Coder does not create latches.

No action required.

Verilog/VHDL: In the senstivity list of a process or always block, do not define constants, use wait statements, or include a signal that is not read inside that block.

HDL Coder generates code that complies with the use of these constructs inside a process block (VHDL) or an always block (Verilog).

No action required.

Verilog: Do not describe multiple event expressions with always constructs.

HDL Coder does not describe more than one event expression in an always construct.

No action required.

Verilog: Do not use nonblocking assignments in combinational always blocks, or when assigning initial values in always constructs of sequential blocks.

Your design uses constructs that generate Verilog code with nonblocking assignments in combinational always blocks or assigns initial values in always constructs of sequential blocks.

Update your MATLAB^® algorithm or Stateflow^® design so that the generated Verilog code does not use these constructs.

Verilog/VHDL: Do not assign a signal more than once in an always construct for sequential circuits.

In an always construct for sequential circuits, HDL Coder does not perform multiple assignments to a signal.

No action required.

Verilog/VHDL: In flip-flop description, do not use quasi-continuous assignments, deassign statements, blocking assignments, variable assignment statements, or stable attribute.

HDL Coder does not introduce any additional data or add these constructs when generating flip-flops in process blocks (VHDL) or always blocks. (Verilog)

No action required.

Verilog/VHDL: Only flip-flop data paths can have delays. The delay values must be integral and non-negative.

HDL Coder does not generate code that uses DELAY attributes for the DUT. The generated testbench can contain DELAY attributes.

No action required.

Verilog/VHDL: Check the logic level of the reset signal as specified in the sensitivity list of the always block.

HDL Coder uses posedge or negedge to denote transitions at clock edges in the generated code.

No action required.

Verilog/VHDL: A flip-flop should not have two asynchronous resets. Do not use functions in the asynchronous reset description.

HDL Coder does not generate multiple asynchronous resets. The generated code can contain multiple synchronous resets.

No action required.

VHDL: Do not use wait constructs.

HDL Coder does not use wait constructs.

No action required.

VHDL: Functions 'rising_edge' or 'falling_edge' should not be used in the design.

By default, HDL Coder uses the event syntax for clock events.

By using the UseRisingEdge property, you can specify whether to use the rising_edge or falling_edge to detect clock transitions.

To fix this error, you can control the UseRisingEdge property such that the generated code uses the event syntax.

Verilog/VHDL: Use blocking assignment in flip-flop description. Do not use blocking and nonblocking assignments together in the same always block.

HDL Coder complies with this rule.

No action required.

VHDL: Variables, if used, must be assigned to a signal before the end of the process.

The generated HDL code does not contain dead code, so HDL Coder complies with this rule.

No action required.

Verilog/VHDL: Do not use edges of multiple clocks or both edges of the same clock in an always block. Do not describe multiple clock edges in a single process/always block for same edge of a single clock.

HDL Coder uses the rising edge or falling edge of the clock, but does not use both edges of the clock.

No action required.

Verilog/VHDL: Minimize, and if possible, remove clock enable signals and reset signal on networks.

If your design generates code that uses clock enables and reset signals on networks, HDL Coder generates an error.

To minimize clock enables in the generated HDL code, in the HDL coding standard customization properties, enable the MinimizeClockEnableCheck property.

To remove reset signals on the networks, in the HDL coding standard customization properties, enable the RemoveResetCheck setting.

Verilog/VHDL: Do not use asynchronous reset signals.

Your Simulink^® model design or MATLAB code uses asynchronous reset signals.

To avoid this violation, use synchronous reset signals for your design. In the Configuration Parameters dialog box, set Reset type to Synchronous.

Verilog/VHDL: Do not specify flip-flop or RAM initial value using initial construct.

The generated HDL code for your design contains an unsynthesizable initial statement.

Disable the Initialize block RAM or Initialize all RAM blocks option in the HDL Workflow Advisor.

You can disable this rule checking by using the InitialStatements property of the HDL coding standard customization object.

Verilog/VHDL: Do not use multiple resets or mix descriptions of flip-flops with and without asynchronous reset in the same process/always block.

HDL Coder complies with this rule.

No action required.

Verilog/VHDL: Latch descriptions should not have asynchronous set or asynchronous reset, or be mixed with other descriptions in the same module.

HDL Coder does not create latches in the generated code.

No action required.

Verilog/VHDL: Do not use combinational loops that contain latches or level two latches in the same phase clock.

By default, HDL Coder does not create combinational loops. If your MATLAB algorithm contains combinational loops, the generated HDL code can use combinational loops.

Update your MATLAB code so that the generated HDL code does not contain any combinational loops.

Verilog/VHDL: Tristate descriptions must not be mixed with other descriptions in the same module and should not contain logic in tristate enable conditions.

HDL Coder does not create latches or tristate buffers in the generated code.

No action required.

Verilog/VHDL: Tristate bus must not be driven by more than specified number of drivers. A net that is not tristated or a signal without a resolution function must not have multiple drivers.

HDL Coder does not create latches or tristate buffers in the generated code.

No action required.

Verilog/VHDL: Inout port should not be directly connected to input/output. Do not use tristate output in an if conditional expression or in the selection expression of a case statement that assigns a fixed value in others choice.

By default, HDL Coder does not connect input or output ports directly to bidirectional ports.

In your Simulink model, on the HDL block properties for the input or output port, if you set BidirectionalPort to on, the generated HDL code can directly connect inout to input or output ports.

In your Simulink model, on the HDL block properties for the input or output port, set BidirectionalPort to off.

Verilog/VHDL: Logic directly driven by tristate nets should be in a separate module.

HDL Coder does not have tristate nets in the generated HDL code.

No action required.

Verilog/VHDL: Do not describe more than one statement (if/case/while/for/loop) separately within a single always or process block.

The generated HDL code for your design contains more than one conditional statement (if-else, case, and loops) that is described separately within a process block (for VHDL code) or an always block (for Verilog code).

Update your design so that there is not more than one conditional statement that is described separately in a process block.

You can customize this rule by using the ConditionalRegionCheck property of the HDL coding standard customization object.

Verilog/VHDL: A variable in the sensitivity list is modified inside the same process or always block.

HDL Coder does not modify the variables in the sensitivity list, including clock, reset, and enable signals.

No action required.

Verilog/VHDL: Avoid describing conditions that will not be executed.

The generated HDL code does not contain dead code, or result in conditions that are not executed.

No action required.

Verilog/VHDL: Nesting in if-else constructs should not be deeper than N levels. Where feasible case statements should be used, rather than if-else statements, if performance is important.

The MATLAB code contains an if-elseif statement with more than N levels of nesting. By default, N is 3.

Modify if-elseif statements in your MATLAB code so there are N or fewer levels of nesting.

For example, the following if-elseif pseudocode contains three levels of nesting:

if ...
   if ...
      if ...
      else
   else
else

You can customize this rule by using the IfElseNesting property of the HDL coding standard customization object.

The generated HDL code contains an if-elseif statement with more than seven branches.

Modify if-elseif statements in your MATLAB code so that the number of branches is seven or fewer.

For example, the following if-elseif pseudocode contains three branches:

if ...
elseif ...
elseif ...
else

You can customize this rule by using the IfElseChain property of the HDL coding standard customization object.

Verilog/VHDL: Attach begin-end to "if" statements.

The generated HDL code complies with these code constructs.

No action required.

Verilog: Do not use fork-join constructs.

Verilog/VHDL: case constructs should not have overlapping clause conditions. Do not use full_case directive.

The generated HDL code complies with these constructs for case statements and does not use the full_case directive.

No action required.

Verilog: Do not use //synposys full_case pragma when all conditions are not described as case clause or the default clause is missing.

HDL Coder describes all possible cases in a case statement so that the synthesis tool does not infer a latch.

No action required.

Verilog/VHDL: A signal that is assigned don't care value in a case default clause should not be used in if conditions, ternary and case constructs.

HDL Coder does not use a signal that is assigned a don’t care value in the default clause.

No action required.

Verilog/VHDL: Default clause in case construct must be the last clause.

To avoid latch inference, HDL Coder describes all possible cases, including the default clause.

No action required.

Verilog/VHDL: Do not use a signal to which don't care is assigned for selection expression of casex statements or case statements that do not assign 'X' in default clause.

HDL Coder does not use don’t care values, and explores the entire space of an n-bit select signal.

No action required.

Verilog: Design should not use casex or casez constructs. casex or casez constructs must contain a dont-care condition, and not have complex clause conditions. The don't care condition in casex or casez branches must follow proper coding style.

HDL Coder does not generate casex or casez constructs, so that it complies with this rule.

No action required.

Verilog: Do not use parallel_case directive. In a case clause condition, do not use fixed values, variables, expressions, and logical, arithmetic, bitwise, or reduction operations.

HDL Coder does not use the parallel_case directive and generates code that complies with these constructs.

No action required.

Verilog: Loop variable and terminating condition of "for" construct must have constant initial value.

HDL Coder does not generate casex or casez constructs so that it complies with this rule.

No action required.

Verilog: Loop variable of "for" construct must have a constant value inside the construct and must not be used outside the construct.

HDL Coder generates the right loop constructs and complies with this rule.

No action required.

Verilog: The loop termination condition must not be a constant.

Verilog/VHDL: Separate for loops must be used in reset and logic parts of flip-flop descriptions.

HDL Coder uses separate for loops in the reset and logic parts of flip-flop descriptions.

No action required.

VHDL: Exit or next statement must not be used in a for loop.

The generated code contains for loops only when HDL Coder knows the number of iterations. When the loop is executing, HDL Coder does not exit from the for loop,

No action required.

Verilog: Signals must not be compared with X or Z, or values containing X or Z.

By default, HDL Coder does not generate code that contains these constructs.

If your Simulink model design uses Constant blocks with Architecture set to Logic Value and uses these constructs, the coder displays this message.

Update your Simulink model design so that the Constant blocks do not use these constructs when Architecture is set to Logic Value. Alternatively, change the Architecture to Constant.

Verilog/VHDL: Do not assign X except for the others clause of case statements.

By default, HDL Coder does not use X in the others clause of case statements. In certain cases, if the generated code does not comply with 2.J.A.4a-c, HDL Coder can assign X in the others clause.

Update your Simulink model design so that the generated HDL code does not use constructs that rule 2.J.A.4a-c specifies.

Verilog: Do not use values containing 'X' or 'Z'.

If your design uses unknown or high-impedance constants, HDL Coder displays a warning.

Update your Simulink model or MATLAB algorithm so that there are no high-impedance constants.

VHDL: Do not use values including 'X','Z','U''-','W','H','L', or constants that contain the values 'X','Z','U''-','W','H','L'.

Verilog: Do not use RAM output signals for a conditional expression of if statements, or selection expression of case statements that assign 'x' in the default clause.

By default, HDL Coder complies with this rule. If your Simulink model uses RAM output signals with a Switch or Multiport switch block, the generated HDL code can use these constructs.

Update your Simulink model so that there are no RAM output signals to Switch or Multiport switch blocks.

Verilog/VHDL: Do not perform logical negation on vectors.

HDL Coder does not perform logical negation on vectors.

No action required.

Verilog/VHDL: Bitwidths of operands of a relational or logical operator must match.

HDL Coder ensures that the data types of the operands match in a relational or logical expression.

No action required.

Verilog/VHDL: Bitwidths should be specified for conditional expression.

Verilog/VHDL: Take care when assigning integer to reg or wire, and when comparing negative value reg and integer variables. Integer objects must not be assigned negative values.

HDL Coder complies with this rule.

No action required.

VHDL: Signed data type must be used in signed operation and std_logic_vector calling std_logic_unsigned package must be used in unsigned operation.

HDL Coder complies with this rule.

No action required.

VHDL: Function To_stdlogicvector should not be used in the design.

HDL Coder does not use the function To_stdlogicvector in the code.

No action required.

Verilog: Do not describe arithmetic operators with conditional operators(?) in assign statement.

HDL Coder complies with this rule.

No action required.

The generated HDL code contains a multiplication operator (*) where the output of the multiplication has a bitwidth of 16 or greater.

In your design, implement multiplications by using a shift-and-add algorithm, or ensure that the data size of the output of a multiplication does not require a bitwidth of 16 or greater.

You can customize this rule by using the MultiplierBitWidth property of the HDL coding standard customization object.

HDL Coder identifies the common operational expressions and describes them separately.

No action required.

HDL Coder homogenizes the division operator into a separate statement and complies with this rule.

No action required.

In your design, the left side of the modulus or division operation is greater than 12 bits, or the right side is not a power of two and greater than eight bits.

Update your design so that the number of bits in the operands of the division or modulus operation are within the bounds that the rule specifies.

Your model design contains a Stateflow Chart or State Transition Table that uses more than 40 states.

Update your model design so that there are not more than 40 states.

By default, HDL Coder puts the sequential and combinational parts of a Finite State Machine (FSM) in separate always blocks.

No action required.

HDL Coder does not attach attributes to state variables in the generated code.

No action required.