HDL Coding Standard Customization Properties

Customize HDL coding standard

HDL coding standard customization properties control how HDL Coder™ generates and checks code according to a specified coding standard. By changing property values, you can customize the rules and the appearance of the coding standard report.

Use dot notation to refer to a particular object and property:

cso = hdlcoder.CodingStandard('Industry');
len = cso.SignalPortParamNameLength.length;
cso.ShowPassingRules.enable = false;

The generated code follows the customized coding standard rules as much as possible. However, if following a coding standard rule could cause the HDL code to be uncompilable or unsynthesizable, the coder does not follow the rule.

Coding Standard Report

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`ShowPassingRules` — Show passing rules in coding standard report
structure

Show or do not show passing rules in coding standard report, specified as a structure with the following field.

Field Description

enable

Field	Description
enable	Set to `true` to show passing rules in coding standard report. Set to `false` to show only rules with errors or warnings. The default is `true`.

Set to true to show passing rules in coding standard report.

Set to false to show only rules with errors or warnings.

The default is true.

Basic Coding Rules

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`HDLKeywords` — Check for HDL keywords in design names
structure

Check for HDL keywords in design names (rule CGSL-1.A.A.3), specified as a structure with the following field.

Field Description

enable

Field	Description
enable	Set to `true` to check for HDL keywords in design names. Set to `false` if you do not want to check for HDL keywords in design names. The default is `true`.

Set to true to check for HDL keywords in design names.

Set to false if you do not want to check for HDL keywords in design names.

The default is true.

`DetectDuplicateNamesCheck` — Check for duplicate names
structure

Check for duplicate names in the design (rule CGSL-1.A.A.5), specified as a structure with the following field.

Field Description

enable

Field	Description
enable	Set to `true` to check for duplicate names in the design. Set to `false` if you do not want to check for duplicate names in the design. The default is `true`.

Set to true to check for duplicate names in the design.

Set to false if you do not want to check for duplicate names in the design.

The default is true.

`ModuleInstanceEntityNameLength` — Check module, instance, and entity name length
structure

Check for module, instance, and entity name lengths (rule CGSL-1.A.B.1), specified as a structure with the following fields.

Field Description

enable

Field	Description
enable	Set to `true` to check the length of module, instance, and entity names. Set to `false` if you do not want to check the length of module, instance, and entity names. The default is `true`.
length	Minimum and maximum length of module, instance, and entity name names, specified as a 2-element array of positive integers. The first element is the minimum length, and the second element is the maximum length. The default is [2 32].

Set to true to check the length of module, instance, and entity names.

Set to false if you do not want to check the length of module, instance, and entity names.

The default is true.

length

Minimum and maximum length of module, instance, and entity name names, specified as a 2-element array of positive integers.

The first element is the minimum length, and the second element is the maximum length. The default is [2 32].

`SignalPortParamNameLength` — Check signal, port, and parameter name length
structure

Check for signal, port, and parameter name lengths (rule CGSL-1.A.C.3), specified as a structure with the following fields.

Field Description

enable

Field	Description
enable	Set to `true` to check the length of signal, port, and parameter names. Set to `false` if you do not want to check the length of signal, port, and parameter names. The default is `true`.
length	Minimum and maximum length of signal, port, and parameter names, specified as a 2-element array of positive integers. The first element is the minimum length, and the second element is the maximum length. The default is [2 40].

Set to true to check the length of signal, port, and parameter names.

Set to false if you do not want to check the length of signal, port, and parameter names.

The default is true.

length

Minimum and maximum length of signal, port, and parameter names, specified as a 2-element array of positive integers.

The first element is the minimum length, and the second element is the maximum length. The default is [2 40].

RTL Description Rules

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`MinimizeClockEnableCheck` — Check for clock enable signals
structure

Check for clock enable signals in the generated code (rule CGSL-2.C.C.4), specified as a structure with the following field.

Field Description

enable

Field	Description
enable	Set to `true` to minimize clock enables in the generated code and check for clock enable signals after code generation. Set to `false` if you do not want to check for clock enable signals in the generated code. The default is `false`.

Set to true to minimize clock enables in the generated code and check for clock enable signals after code generation.

Set to false if you do not want to check for clock enable signals in the generated code.

The default is false.

`RemoveResetCheck` — Check for reset signals
structure

Check for reset signals in the design (rule CGSL-2.C.C.5), specified as a structure with the following field.

Field Description

enable

Field	Description
enable	Set to `true` to minimize reset signals in the generated code and check for reset signals after code generation. Set to `false` if you do not want to check for reset signals in the design. The default is `false`.

Set to true to minimize reset signals in the generated code and check for reset signals after code generation.

Set to false if you do not want to check for reset signals in the design.

The default is false.

`AsynchronousResetCheck` — Check for asynchronous reset signals in the generated code
structure

Check for asynchronous reset signals in the generated code (CGSL-2.C.C.6), specified as a structure with the following field.

Field Description

enable

Field	Description
enable	Set to `true` to check for asynchronous reset signals in the generated code. Set to `false` if you do not want to check for asynchronous reset signals in the generated code. The default is `true`.

Set to true to check for asynchronous reset signals in the generated code.

Set to false if you do not want to check for asynchronous reset signals in the generated code.

The default is true.

`MinimizeVariableUsage` — Minimize use of variables
structure

Minimize use of variables (rule CGSL-2.G), specified as a structure with the following field.

Field Description

enable

Field	Description
enable	Set to `true` to minimize use of variables. Set to `false` if you do not want to minimize use of variables. The default is `false`.

Set to true to minimize use of variables.

Set to false if you do not want to minimize use of variables.

The default is false.

`ConditionalRegionCheck` — Check for length of conditional statements in a process or always block
structure

Check for length of conditional statements (if-else, case, and loops) which are described separately in a process block or an always block (rule CGSL-2.F.B.1), specified as a structure with the following fields.

Field Description

enable

Field	Description
enable	Set to `true` to check length of conditional statements. Set to `false` if you do not want to check the length of conditional statements. The default is `true`.
length	Number of conditional statements which are described separately within a process block (`VHDL`) or an always block (`Verilog`). The default is 1.

Set to true to check length of conditional statements.

Set to false if you do not want to check the length of conditional statements.

The default is true.

length

Number of conditional statements which are described separately within a process block (VHDL) or an always block (Verilog).

The default is 1.

`IfElseNesting` — Check if-else statement nesting depth
structure

Check for if-else statement nesting depth (rule CGSL-2.G.C.1a), specified as a structure with the following fields.

Field Description

enable

Field	Description
enable	Set to `true` to check if-else statement nesting depth. Set to `false` if you do not want to check if-else statement nesting depth. The default is `true`.
depth	Maximum if-else statement nesting depth, specified as a positive integer. The default is 3.

Set to true to check if-else statement nesting depth.

Set to false if you do not want to check if-else statement nesting depth.

The default is true.

depth

Maximum if-else statement nesting depth, specified as a positive integer.

The default is 3.

`IfElseChain` — Check if-else statement chain length
structure

Check for if-else statement chain length (rule CGSL-2.G.C.1c), specified as a structure with the following fields.

Field Description

enable

Field	Description
enable	Set to `true` to check if-else statement chain length. Set to `false` if you do not want to check if-else statement chain length. The default is `true`.
length	Maximum length of if-else statement chain, specified as a positive integer. The default is 7.

Set to true to check if-else statement chain length.

Set to false if you do not want to check if-else statement chain length.

The default is true.

length

Maximum length of if-else statement chain, specified as a positive integer.

The default is 7.

`MultiplierBitWidth` — Check multiplier bit width
structure

Check for multiplier bit width (rule CGSL-2.J.F.5), specified as a structure with the following fields.

Field Description

enable

Field	Description
enable	Set to `true` to check multiplier bit width. Set to `false` if you do not want to check multiplier bit width. The default is `true`.
width	Maximum multiplier bit width, specified as a positive integer. The default is 16.

Set to true to check multiplier bit width.

Set to false if you do not want to check multiplier bit width.

The default is true.

width

Maximum multiplier bit width, specified as a positive integer.

The default is 16.

RTL Design Rules

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`LineLength` — Check generated code line length
structure

Check for generated code line length (rule CGSL-3.A.D.5), specified as a structure with the following fields.

Field Description

enable

Field	Description
enable	Set to `true` to check line lengths in generated code. Set to `false` if you do not want to check line lengths in generated code. The default is `true`.
length	Maximum number of characters per line in generated code, specified as a positive integer. The default is 110.

Set to true to check line lengths in generated code.

Set to false if you do not want to check line lengths in generated code.

The default is true.

length

Maximum number of characters per line in generated code, specified as a positive integer.

The default is 110.

`NonIntegerTypes` — Check for non-integer constants
structure

Check for non-integer constants (rule CGSL-3.B.D.1), specified as a structure with the following field.

Field Description

enable

Field	Description
enable	Set to `true` to check for non-integer constants. Set to `false` if you do not want to check for non-integer constants. The default is `true`.

Set to true to check for non-integer constants.

Set to false if you do not want to check for non-integer constants.

The default is true.

Documentation

HDL Coding Standard Customization Properties

Coding Standard Report

`ShowPassingRules` — Show passing rules in coding standard report
structure

Basic Coding Rules

`HDLKeywords` — Check for HDL keywords in design names
structure

`DetectDuplicateNamesCheck` — Check for duplicate names
structure

`ModuleInstanceEntityNameLength` — Check module, instance, and entity name length
structure

`SignalPortParamNameLength` — Check signal, port, and parameter name length
structure

RTL Description Rules

`MinimizeClockEnableCheck` — Check for clock enable signals
structure

`RemoveResetCheck` — Check for reset signals
structure

`AsynchronousResetCheck` — Check for asynchronous reset signals in the generated code
structure

`MinimizeVariableUsage` — Minimize use of variables
structure

`ConditionalRegionCheck` — Check for length of conditional statements in a process or always block
structure

`IfElseNesting` — Check if-else statement nesting depth
structure

`IfElseChain` — Check if-else statement chain length
structure

`MultiplierBitWidth` — Check multiplier bit width
structure

RTL Design Rules

`LineLength` — Check generated code line length
structure

`NonIntegerTypes` — Check for non-integer constants
structure

See Also

Topics

HDL Coder Documentation

Support

Documentation

HDL Coding Standard Customization Properties

Coding Standard Report

ShowPassingRules — Show passing rules in coding standard report structure

Basic Coding Rules

HDLKeywords — Check for HDL keywords in design names structure

DetectDuplicateNamesCheck — Check for duplicate names structure

ModuleInstanceEntityNameLength — Check module, instance, and entity name length structure

SignalPortParamNameLength — Check signal, port, and parameter name length structure

RTL Description Rules

MinimizeClockEnableCheck — Check for clock enable signals structure

RemoveResetCheck — Check for reset signals structure

AsynchronousResetCheck — Check for asynchronous reset signals in the generated code structure

MinimizeVariableUsage — Minimize use of variables structure

ConditionalRegionCheck — Check for length of conditional statements in a process or always block structure

IfElseNesting — Check if-else statement nesting depth structure

IfElseChain — Check if-else statement chain length structure

MultiplierBitWidth — Check multiplier bit width structure

RTL Design Rules

LineLength — Check generated code line length structure

NonIntegerTypes — Check for non-integer constants structure

See Also

Topics

HDL Coder Documentation

Support

`ShowPassingRules` — Show passing rules in coding standard report
structure

`HDLKeywords` — Check for HDL keywords in design names
structure

`DetectDuplicateNamesCheck` — Check for duplicate names
structure

`ModuleInstanceEntityNameLength` — Check module, instance, and entity name length
structure

`SignalPortParamNameLength` — Check signal, port, and parameter name length
structure

`MinimizeClockEnableCheck` — Check for clock enable signals
structure

`RemoveResetCheck` — Check for reset signals
structure

`AsynchronousResetCheck` — Check for asynchronous reset signals in the generated code
structure

`MinimizeVariableUsage` — Minimize use of variables
structure

`ConditionalRegionCheck` — Check for length of conditional statements in a process or always block
structure

`IfElseNesting` — Check if-else statement nesting depth
structure

`IfElseChain` — Check if-else statement chain length
structure

`MultiplierBitWidth` — Check multiplier bit width
structure

`LineLength` — Check generated code line length
structure

`NonIntegerTypes` — Check for non-integer constants
structure