The HDL Workflow Advisor is a tool that supports a suite of tasks covering the stages of the FPGA design process. Some tasks perform model validation or checking; others run the HDL code generator or third-party tools. Each folder at the top level of the HDL Workflow Advisor contains a group of related tasks that you can select and run.
For summary information on each HDL Workflow Advisor folder or task, select the folder or task icon and then click the HDL Workflow Advisor Help button.
Set Target: The tasks in this category enable you to select the desired target device and map its I/O interface to the inputs and outputs of your model.
Prepare Model For HDL Code Generation: The tasks in this category check your model for HDL code generation compatibility. The tasks also report on model settings, blocks, or other conditions (such as algebraic loops) that would impede code generation, and provide advice on how to fix such problems.
HDL Code Generation: This category supports all HDL-related options of the Configuration Parameters dialog, including setting HDL code and test bench generation parameters, and generating code, test bench, or a cosimulation model.
FPGA Synthesis and Analysis: The tasks in this category support:
Synthesis and timing analysis through integration with third-party synthesis tools
Back annotation of the model with critical path and other information obtained during synthesis
FPGA-in-the-Loop Implementation: This category implements the phases of FIL, including providing block generation, synthesis, logical mapping, PAR (place-and-route), programming file generation, and a communications channel. These capabilities are designed for a particular board and tailored to your RTL code. An HDL Verifier™ license is required for FIL.
Download to Target: The tasks in this category depend on the selected target device and potentially include:
Generation of a target-specific FPGA programming file
Programming the target device
Generation of a model that contains a Simulink® Real-Time™ interface subsystem
The tasks in the Set Target folder enable you to select a target FPGA device and define the interface generated for the device.
Set Target Device and Synthesis Tool: Select a target FPGA device and synthesis tools.
Set Target Reference Design: For IP Core
Generation workflow, select a reference design for your
target device.
Set Target Interface: For IP Core
Generation, FPGA Turnkey, and
Simulink Real—Time FPGA I/O workflows,
use the Target Platform Interface Table to assign each port on your DUT to
an I/O resource on the target device.
Set Target Frequency: Select the target clock rate for the FPGA implementation of your design.
For summary information on each Set Target task, select the task icon and then click the HDL Workflow Advisor Help button.
The Set Target Device and Synthesis Tool task enables you to select an FPGA target device and an associated synthesis tool from a pulldown menu that lists the devices that HDL Workflow Advisor currently supports.
This task displays the following options:
Target Workflow: A pulldown menu that lists the possible workflows that HDL Workflow Advisor supports. Choose from:
Generic ASIC/FPGA
FPGA-in-the-loop
FPGA Turnkey
Simulink Real-Time FPGA I/O
IP Core Generation
Customization for the USRP device
Software Defined Radio
Target platform: A pulldown menu that lists the devices the HDL Workflow Advisor currently supports. Not available for the Generic ASIC/FPGA workflow.
Synthesis tool: Select a synthesis tool, then select the Family, Device, Package, and Speed for your synthesis target.
If your synthesis tool is not one of the Synthesis tool options, see Synthesis Tool Path Setup. After you set up your synthesis tool path, click Refresh to make the tool available in the HDL Workflow Advisor.
Project folder: Specify the project folder name.
Tool version: This check box displays the current synthesis tool version.
Note
If you select Intel Quartus Pro or
Microsemi Libero SoC as the
Synthesis tool, you can
only run the Generic
ASIC/FPGA workflow. When you use these tools, the
Annotate Model with Synthesis Result task is not
available. In this case, you can run the workflow to synthesis and then view
the timing reports to see the critical path.
The Set Target Reference Design task displays the reference design input parameters and the tool version. A Reference design parameters section displays any custom parameters that you specify for the reference design.
The task displays the following options:
Reference design: A pulldown menu that lists the reference designs that HDL Coder™ supports and any custom reference designs that you specify. To learn more about creating a custom board and reference design, see Board and Reference Design Registration System.
Reference design tool version: A text box that displays the current reference design tool version. It is recommended to use a reference design tool version that is compatible with the supported tool version. If there is a tool version mismatch, HDL Coder generates an error when you run this task. The tool version mismatch can potentially cause the Create Project task to fail.
If you select the Ignore tool version mismatch check box, HDL Coder generates a warning instead of an error. You can attempt to continue with creating the reference design project.
Reference design parameters: Lists the parameters of the reference design. These can be parameters available with the default reference designs that HDL Coder supports, or parameters that you define for your custom reference design. For more information, see Define Custom Parameters and Callback Functions for Custom Reference Design.
The Set Target Interface task displays properties of input and output ports on your DUT, and enables you to map these ports to I/O resources on the target device.
Set Target Interface displays the Target Platform Interface Table, which shows:
The name, port type (input or output), and data type for each port on your DUT.
A pulldown menu listing the available I/O resources for the target device.
These resources are device-specific. For detailed information on each resource, see the documentation for your FPGA development board.
Specify the target frequency for these workflows:
Generic ASIC/FPGA: To specify the target
frequency that you want your design to achieve. HDL Coder generates a timing constraint file for that clock
frequency and adds the constraint to the FPGA synthesis tool project
that you create in the Create Project task. If the
target frequency is not achievable, the synthesis tool generates an
error. Target frequency is not supported with Microsemi®
Libero® SoC.
IP Core Generation: To specify the target
frequency for HDL Coder to modify the clock module setting in the reference design
to produce the clock signal with that frequency. Enter a target
frequency value that is within the Frequency Range
(MHz). If you do not specify the target frequency,
HDL Coder uses the Default (MHz) target
frequency.
Simulink Real-Time FPGA I/O: For Speedgoat
boards that are supported with Xilinx ISE,
specify the target frequency to generate the clock module to produce the
clock signal with that frequency.
The Speedgoat boards that are supported with Xilinx
Vivado use the IP Core
Generation workflow infrastructure. Specify the target
frequency for HDL Coder to modify the clock module setting in the reference design
to produce the clock signal with that frequency. Enter a target
frequency value that is within the Frequency Range
(MHz). If you do not specify the target frequency,
HDL Coder uses the Default (MHz) target
frequency.
FPGA Turnkey: To generate the clock module
to produce the clock signal with that frequency automatically.
Select a processor-FPGA synchronization mode, and map your DUT input and output ports to I/O resources on the target device.
For Processor/FPGA synchronization, select:
Free running if you do not want your processor and FPGA to be automatically synchronized.
Coprocessing – blocking if you want HDL Coder to generate synchronization logic for the FPGA automatically, so that the processor and FPGA run in tandem. Select this mode when FPGA execution time is short relative to the processor sample time, and you want the FPGA to complete before the processor continues.
Coprocessing – nonblocking with delay (not
supported for IP Core Generation
workflow) if you want HDL Coder to generate synchronization logic for the FPGA
automatically, so that the processor and FPGA run in tandem. Select
this mode when the FPGA processing time is long relative to the
processor sample time, or you do not want the processor to wait for
the FPGA to finish before the processor continues.
This setting is saved with the model as the
ProcessorFPGASynchronization HDL block property for the
DUT block.
The Target Platform Interface Table shows:
The name, port type (input or output), and data type for each port on your DUT.
A pulldown menu listing the available I/O resources for the target device.
These resources are device-specific. For detailed information on each resource, see the documentation for your FPGA development board.
Select a processor-FPGA synchronization mode, and map your DUT input and output ports to I/O resources on the target device. Optionally, specify a reference design.
Reference design: Select the predefined embedded system integration project into which HDL Coder inserts your generated IP core.
Reference design path: Enter the path to your downloaded reference design components. This field is available only if the specified Reference design requires downloadable components.
For Processor/FPGA synchronization, select:
Free running if you do not want your processor and FPGA to be automatically synchronized.
Coprocessing – blocking if you want HDL Coder to generate synchronization logic for the FPGA automatically, so that the processor and FPGA run in tandem. Select this mode when FPGA execution time is short relative to the processor sample time, and you want the FPGA to complete before the processor continues.
Coprocessing – nonblocking with delay (not
supported for IP Core Generation
workflow) if you want HDL Coder to generate synchronization logic for the FPGA
automatically, so that the processor and FPGA run in tandem. Select
this mode when the FPGA processing time is long relative to the
processor sample time, or you do not want the processor to wait for
the FPGA to finish before the processor continues.
This setting is saved with the model as the
ProcessorFPGASynchronization HDL block property for the
DUT block.
The Target Platform Interface Table shows:
The name, port type (input or output), and data type for each port on your DUT.
A dropdown menu listing the available I/O resources for the target device.
These resources are device-specific. For detailed information on each resource, see the documentation for your FPGA development board.
The tasks in the Prepare Model For HDL Code Generation folder check the model for compatibility with HDL code generation. If a check encounters a condition that would raise a code generation warning or error, the right pane of the HDL Workflow Advisor displays information about the condition and how to fix it. The Prepare Model For HDL Code Generation folder contains the following checks:
Check Global Settings: Check model parameters for compatibility with HDL code generation.
Check Algebraic Loops: Check the model for algebraic loops.
Check Block Compatibility: Check that blocks in the model support HDL code generation.
Check Sample Times: Check the solver options, tasking mode, and rate transition diagnostic settings, given the model's sample times.
Check FPGA-in-the-Loop Compatibility: Check model compatibility with FPGA-in-the-loop, specifically:
Not allowed: sink/source subsystems, single/double data types, zero sample time
Must be present: HDL Verifier license
This option is available only if you select
FPGA-in-the-Loop for Target workflow.
Check USRP Compatibility: The model must have two input ports and two output ports of signed 16-bit signals.
This option is available only if you select Customization for
the USRP Device for Target workflow.
For summary information on each Prepare Model For HDL Code Generation task, select the task icon and then click the HDL Workflow Advisor Help button.
Check Global Settings checks model-wide parameter settings for HDL code generation compatibility.
This check examines the model parameters for compatibility with HDL code generation and flags conditions that would raise an error or a warning during code generation. The HDL Workflow Advisor displays a table with the following information about each condition detected:
Block: Hyperlink to the model configuration dialog box page that contains the error or warning condition
Settings: Name of the model parameter that caused the error or warning condition
Current: Current value of the setting
Recommended: Recommended value of the setting
Severity: Severity level of the warning or error
condition. Minimally, you should fix settings that are tagged as
error.
To set reported settings to their recommended values, click the Modify All button. You can then run the check again and proceed to the next check.
Detect algebraic loops in the model.
The HDL Coder software does not support HDL code generation for models in which algebraic loop conditions exist. Check Algebraic Loops examines the model and fails the check if it detects an algebraic loop. Eliminate algebraic loops from your model before proceeding with further HDL Workflow Advisor checks or code generation.
Check the DUT for unsupported blocks.
Check Block Compatibility checks blocks within the DUT for compatibility with HDL code generation. The check fails if it encounters blocks that HDL Coder does not support. The HDL Workflow Advisor reports incompatible blocks, including the full path to each block.
Check the solver, sample times, and tasking mode settings for the model.
Check Sample Times checks the solver options, sample times, tasking mode, and rate transition diagnostics for HDL code generation compatibility. Solver options that the HDL Coder software requires or recommends are:
Type: Fixed-step. (The coder currently supports
variable-step solvers under limited conditions. See
hdlsetup for details.)
Solver: Discrete (no continuous states). Other fixed-step solvers could be selected, but this option is usually the best one for simulating discrete systems.
Tasking mode:
SingleTasking. The coder does not
currently support models that execute in multitasking mode. Do not set
Tasking mode to
Auto.
Multitask rate transition and Single
task rate transition diagnostic options: set to
Error.
HDL Verifier checks model for compatibility with FPGA-in-the-loop processing.
Prepare DUT For FIL Interface Generation (HDL Verifier).
The tasks in the HDL Code Generation folder enable you to:
Set and validate HDL code and test bench generation parameters. Most parameters of the HDL Code Generation pane of the Configuration Parameters dialog box and the Model Explorer are supported.
Generate any or all of:
RTL code
RTL test bench
Cosimulation model
SystemVerilog DPI test bench
To run the tasks in the HDL Code Generation folder automatically, select the folder and click Run All.
Tip
After each task in this folder runs, HDL Coder updates the Configuration Parameters dialog box and the Model Explorer.
The tasks in the Set Code Generation Options folder enable you to set and validate HDL code and test bench generation parameters. Each task of the Set Code Generation Options folder supports options of the HDL Code Generation pane of the Configuration Parameters dialog box and the Model Explorer. The tasks are:
Set Basic Options: Set parameters that affect overall code generation.
Set Report Options: Set parameters that affect the code generation report.
Set Advanced Options: Set parameters that specify detailed characteristics of the generated code, such as HDL element naming and whether certain optimizations apply.
Set Optimization Options: Set parameters that specify optimizations such as resource sharing and pipelining to improve area and timing.
Set Testbench Options: Set options that determine characteristics of generated test bench code.
To run the tasks in the Set Code Generation Options folder automatically, select the folder and click Run All.
Set parameters that affect overall code generation.
The Set Basic Options task sets options that are fundamental to HDL code generation. These options include selecting the DUT and selecting the target language. The basic options are the same as those found in the top-level HDL Code Generation pane of the Configuration Parameters dialog box, except that the Code generation output group is omitted.
Set parameters that specify the sections that you want to see in the Code Generation Report.
The options are same as those found in the HDL Code Generation > Report pane of the Configuration Parameters dialog box and the Model Explorer.
Set parameters that specify detailed characteristics of the generated code.
The advanced options are the same as those found in the HDL Code Generation > Global Settings pane of the Configuration Parameters dialog box and the Model Explorer.
Set parameters that specify optimizations such as resource sharing and pipelining to improve area and timing.
The optimization options are the same as those found in the HDL Code Generation > Target and Optimizations pane of the Configuration Parameters dialog box and the Model Explorer.
Set options that determine characteristics of generated test bench code.
The test bench options are the same as those found in the HDL Code Generation > Test Bench pane of the Configuration Parameters dialog box and the Model Explorer.
Generate RTL code and HDL top-level wrapper.
The Generate RTL Code task generates RTL code and an HDL top-level wrapper for the DUT subsystem. It also generates a constraint file that contains pin mapping information and clock constraints.
Select and initiate generation of RTL code, RTL test bench, and cosimulation model.
The Generate RTL Code and Testbench task enables choosing what type of code or model that you want to generate. You can select any combination of the following:
Generate RTL code: Generate RTL code in the target language.
Generate test bench: Generate the test bench(es) selected in Set Testbench Options.
Generate validation model: Generate a validation model that highlights generated delays and other differences between your original model and the generated cosimulation model. With a validation model, you can observe the effects of streaming, resource sharing, and delay balancing.
The validation model contains the DUT from the original model and the DUT from the generated cosimulation model. Using the validation model, you can verify that the output of the optimized DUT is bit-true to the results produced by the original DUT.
Generating a Simulink Model for Cosimulation with an HDL Simulator (Filter Design HDL Coder).
Run this step to verify the generated HDL using cosimulation between the HDL Simulator and the Simulink test bench. This step shows only if you selected Cosimulation model, and specified an HDL simulator, in Set Testbench Options.
Select and initiate generation of RTL code and custom IP core.
In the Generate RTL Code and IP Core task, specify characteristics of the generated IP core:
IP core name: Enter the IP core name.
This setting is saved with the model as the
IPCoreName HDL block property for the DUT
block.
IP core version: Enter the IP core version number. HDL Coder appends the version number to the IP core name to generate the output folder name.
This setting is saved with the model as the
IPCoreVersion HDL block property for the DUT
block.
IP core folder (not editable): HDL Coder generates the IP core files in the output folder shown, including the HTML documentation.
IP repository: If you have an IP repository folder, enter its path manually or by using the Browse button. The coder copies the generated IP core into the IP repository folder.
Additional source files: If you are using a black box interface in your design to include existing Verilog® or VHDL® code, enter the file names. Enter each file name manually, separated with a semicolon (;), or by using the Add button. The source file language must match your target language.
This setting is saved with the model as the
IPCoreAdditionalFiles HDL block property for
the DUT block.
FPGA Data Capture buffer size: The buffer size
uses values that are 128*2^n, where
n is an integer. By default, the buffer size is
128 (n=0). The maximum value
of n is 13, which means that the
maximum value for buffer size is 1048576
(=128*2^13).
This setting is saved with the model as the
IPDataCaptureBufferSize HDL block property for
the DUT block.
Generate IP core report: Leave this option selected to generate HTML documentation for the IP core.
Enable readback on AXI4 slave write registers: Select this option if you want to read back the value that is written to the AXI4 slave registers by using the AXI4 slave interface. When you run this task, the code generator adds a mux for each AXI4 register in the address decoder logic. This mux compares the address that the data is written to when reading the values. If you are reading from multiple AXI4 slave registers, the readback logic becomes a long mux chain that can affect synthesis frequency.
This setting is saved with the model as the
AXI4RegisterReadback HDL block property for the
DUT block.
Generate default AXI4 slave interface: Leave this option selected if you want to generate an HDL IP core with the AXI4 slave interface for signals such as clock, reset, ready, timestamp, and so on. If you want to generate a generic HDL IP core without any AXI4 slave interfaces, clear this check box. In addition, make sure that you do not map any of the DUT ports to AXI4 or AXI4-Lite interfaces. You can only map the ports to External or Internal IO interfaces, or AXI4-Stream interface with TLAST mapping.
This setting is saved with the model as the
GenerateDefaultAXI4Slave HDL block property for
the DUT block.
Create projects for supported FPGA synthesis tools, perform FPGA synthesis, mapping, and place/route tasks, and annotate critical paths in the original model
The tasks in the FPGA Synthesis and Analysis folder enable you to:
Create FPGA synthesis projects for supported FPGA synthesis tools.
Launch supported FPGA synthesis tools, using the project files to perform synthesis, mapping, and place/route tasks.
Annotate your original model with critical path information obtained from the synthesis tools.
For a list of supported third-party synthesis tools, see Third-Party Synthesis Tools and Version Support.
The tasks in the folder are:
Create Project
Perform Synthesis and P/R
Annotate Model with Synthesis Result
Create FPGA synthesis project for supported FPGA synthesis tool.
This task creates a synthesis project for the selected synthesis tool and loads the project with the HDL code generated for your model.
When the project creation completes, the HDL Workflow Advisor displays a link to the project in the right pane. Click this link to view the project in the synthesis tool project window.
Select a synthesis objective to generate tool-specific
optimization Tcl commands for your project. If you specify
None,
no Tcl commands are
generated.
To learn how the synthesis objectives map to Tcl commands, see Synthesis Objective to Tcl Command Mapping.
Enter additional HDL source files you want included in your synthesis project. Enter each file name manually, separated with a semicolon (;), or by using the Add Source button.
For example, you can include HDL source files (.vhd or .v) or a constraint file (.ucf or .sdc).
Enter additional project creation Tcl files you want to include in your synthesis project. Enter each file name manually, separated with a semicolon (;), or by using the Add Tcl button.
For example, you can include a Tcl script (.tcl) to execute after creating the project.
Launch supported FPGA synthesis tools to perform synthesis, mapping, and place/route tasks.
The tasks in the Perform Synthesis and P/R folder enable you to launch supported FPGA synthesis tool and:
Synthesize the generated HDL code.
Perform mapping and timing analysis.
Perform place and route functions.
For a list of supported third-party synthesis tools, see Third-Party Synthesis Tools and Version Support.
Launch supported FPGA synthesis tool and synthesize the generated HDL code.
The Perform Logic Synthesis task:
Launches the synthesis tool in the background.
Opens the previously generated synthesis project, compiles HDL code, synthesizes the design, and emits netlists and related files.
Displays a synthesis log in the Result subpane.
Launches supported FPGA synthesis tool and maps the synthesized logic design to the target FPGA.
The Perform Mapping task:
Launches the synthesis tool in the background.
Runs a mapping process that maps the synthesized logic design to the target FPGA.
Emits a circuit description file for use in the place and route phase.
Also emits pre-routing timing information for use in critical path analysis and back annotation of your source model.
Displays a log in the Result subpane.
Enable Skip pre-route timing analysis if your tool does not support early timing estimation. When this option is enabled, the Annotate Model with Synthesis Result task sets Critical path source to post-route.
Launches the synthesis tool in the background and runs a Place and Route process.
The Perform Place and Route task:
Launches the synthesis tool in the background.
Runs a Place and Route process that takes the circuit description produced by the previous mapping process, and emits a circuit description suitable for programming an FPGA.
Also emits post-routing timing information for use in critical path analysis and back annotation of your source model.
Displays a log in the Result subpane.
If you select Skip this task , the HDL Workflow Advisor
executes the workflow, but omits the Perform Place and
Route task, marking it Passed. You might want
to select Skip this task if you prefer to do place and
route work manually.
If Perform Place and Route fails, but you want to use the post-mapping timing results to find critical paths in your model, you can select Ignore place and route errors and continue to the Annotate Model with Synthesis Result task.
Launches Xilinx® Vivado® and executes the Vivado Synthesis step.
Enable Skip pre-route timing analysis if you do not want to do early timing estimation.
Launches Xilinx Vivado and executes the Vivado Implementation step.
If you select Skip this task , the HDL Workflow Advisor
omits the Run Implementation task, marking it
Passed. Select Skip this task if you
prefer to do place and route work manually.
If Run Implementation fails, you can select Ignore place and route errors and continue to the Annotate Model with Synthesis Result task.
If there are timing failures during this task, the task does not fail. You must check the timing report for timing failures.
Analyzes pre- or post-routing timing information and visually highlights critical paths in your model
The Annotate Model with Synthesis Result task helps you to identify critical paths in your model. At your option, the task analyzes pre- or post-routing timing information produced by the Perform Synthesis and P/R task group, and visually highlights one or more critical paths in your model.
Note
If you select Intel Quartus Pro or
Microsemi Libero SoC as the
Synthesis tool, the Annotate Model with
Synthesis Result task is not available. In this case, you can
run the workflow to synthesis and then view the timing reports to see the
critical path.
If Generate FPGA top level wrapper is selected in the Generate RTL Code and Testbench task, Annotate Model with Synthesis Result is not available. To perform back-annotation analysis, clear the check box for Generate FPGA top level wrapper.
Select pre-route or post-route.
The pre-route option is unavailable when Skip pre-route timing analysis is enabled in the previous task group.
You can annotate up to 3 critical paths. Select the number of paths you want to annotate.
Show critical paths, including duplicate paths.
Show only the first instance of a path that is duplicated.
Annotate the cumulative timing delay on each path.
Show the endpoints of each path, but omit the connecting signal lines.
When the Annotate Model with Synthesis Result task runs to completion, HDL Coder displays the DUT with critical path information highlighted.
The Download to Target folder supports the following tasks:
Generate Programming File: Generate an FPGA programming file.
Program Target Device: Download generated programming file to the target development board.
Generate Simulink Real-Time Interface (for Speedgoat target devices only): Generate a model that contains a Simulink Real-Time interface subsystem.
For summary information on each Download to Target task, select the task icon and then click the HDL Workflow Advisor Help button.
The Generate Programming File task generates an FPGA programming file that is compatible with the selected target device.
The Program Target Device task downloads the generated FPGA programming file to the selected target device.
Before executing the Program Target Device task, make sure that your host PC is properly connected to the target development board via the required programming cable.
The Generate Simulink Real-Time Interface task generates a model containing an interface subsystem that you can plug in to a Simulink Real-Time model.
The naming convention for the generated model is:
gm_fpgamodelname_slrt
where fpgamodelname is the name of the original model.
You can save the current settings of the HDL Workflow Advisor to a named restore point. Later, you can restore the same settings by loading the restore point data into the HDL Workflow Advisor.
Set FIL options and run FIL processing.
Set connection type, board IP, and MAC addresses and select additional files, if required.
Select either JTAG (Altera® boards only) or
Ethernet.
Use this option for setting the IP address of the board if it is not the default IP address (192.168.0.2).
Under most circumstances, you do not need to change the Board MAC address. You will need to do so if you connect more than one FPGA development board to a single computer (for which you must have a separate NIC for each board). You must change the Board MAC address for additional boards so that each address is unique.
Select additional source files for the HDL design that is to be verified on the FPGA board, if required. HDL Workflow Advisor attempts to identify the file type; change the file type in the File Type column if it is incorrect.
During the build process, the following actions occur:
FPGA-in-the-loop generates a FIL block named after the top-level module and places it in a new model.
After new model generation, FIL opens a command window. In this window, the FPGA design software performs synthesis, fit, place-and-route, timing analysis, and FPGA programming file generation. When the process completes, a message in the command prompts you to close the window.
FPGA-in-the-loop builds a testbench model around the generated FIL block.
The model must have two input ports and two output ports of signed 16-bit signals.
This step initiates FPGA programming file creation. For Input Parameters, enter the path to the Ettus Research™ USRP™ FPGA files you previously downloaded. If you have not yet downloaded these files, see the Support Package for USRP Radio documentation.
When this step completes, see the instructions for downloading the programming file to the FPGA and running the simulation in the Support Package for USRP Radio documentation for FPGA Targeting.
The DUT must adhere to certain signal interface requirements. During Check SDR Compatibility, the following interface checks are performed (Inputs and Outputs go through the same checks).
Must include single complex signal, two scalar signals, or single vectored signal of size 2
Must have a bitwidth of 16
Must be signed
Must be single rate
If have vectored ports must use Scalarize Vectors option
If have multiple rates, must use Single clock
Must use synchronous reset
Must use active-high reset
Must use a user overclocking factor of 1
All error checks are done for a given task run and reported in a table. This allows a single iteration to fix all errors.
The SDR FPGA integrates customer logic as generated in previous steps as well as SDR-specific code to provide data and control paths between an RF board and the host.
This step consists of the following tasks:
Set SDR Options: Choose customization options
Build SDR: Generate FPGA programming file for an SDR target.
Choose customization options for the completion of the SDR FPGA implementation.
RF board for target
Choose one of the following:
Epic Bitshark FMC-1Rx RevB
Epic Bitshark FMC-1Rx RevC
Folder with vendor HDL source code
Specify the folder that contains the RF interface HDL downloaded from the vendor support site. Use Browse to navigate to the correct folder.
User logic synthesis frequency
Specify the maximum frequency at which you want to run your design. This value must be greater than the sampling frequencies for ADC and DAC as specified in the ADI FMCOMMS or Epiq Bitshark™ block.
User logic data path
Select either the Receiver data path or the
Transmitter data path.
Board IP address
Set the board's IP address in this field if it is not the default IP address (192.168.10.1).
Board MAC address
Under most circumstances, you do not need to change the Board MAC address. However, you need to do so if you connect more than one FPGA development board to a single computer (for which you must have a separate NIC for each board). You must change the Board MAC address for additional boards so that each address is unique.
Specify files you want included in the ISE or Vivado project. You should include only file types supported by ISE or Vivado. If an included file does not exist, the HDL Workflow Advisor cannot create the project.
File: Name of file added to design (with Add).
File Type: File type. The software will attempt
to determine the file type automatically, but you may override the
selection. Options are VHDL,
Verilog, EDIF
netlist, VQM netlist,
QSF file,
Constraints, and
Others.
Add: Add a new file to the list.
Remove: Removes the currently selected file from the list.
Up: Moves the currently selected file up the list.
Down: Moves the currently selected file down the list.
Show full paths to source files (checkbox) triggers a full path display. Leaving this box unchecked displays only the file name.
The HDL Workflow Advisor creates a new Xilinx ISE or Vivado project and adds the following:
All the necessary files from the FPGA repository
The generated HDL files for the selected subsystem and algorithm
If no errors are found during FPGA project generation and syntax checking, the FPGA programming file generation process starts. You can view this process in an external command shell and monitor its progress. When the process is finished, a message in the command window prompts you to close the window.
Tasks in this folder integrate your generated HDL IP core with the embedded processor.
Create project for embedded system tool.
In the message window, after the project is generated, you can click the project link to open the generated embedded system tool project.
Embedded design tool.
Folder where your generated project files are saved.
Select a synthesis objective to generate tool-specific
optimization Tcl commands for your project. If you specify
None,
no Tcl commands are
generated.
To learn how the synthesis objectives map to Tcl commands, see Synthesis Objective to Tcl Command Mapping.
Generate a software interface model or script or both with IP core driver blocks for embedded C code generation.
After you generate the software interface model, you can generate C code from it using Embedded Coder® The script contains commands that enable you to connect to the target hardware, and to write to or read from the generated IP core by using AXI driver blocks.
When you clear both the Generate Simulink software interface model and Generate MATLAB software interface script check boxes, this task is skipped.
Operating system: Select your target operating system.
Generate bitstream for embedded system.
Enable this option to run the build process in parallel with MATLAB®. If this option is disabled, you cannot use MATLAB until the build is finished.
To customize your synthesis build, save your custom Tcl commands in a
file and select Custom. Enter the file path
manually or by using the Browse button. The
contents of your custom Tcl file are inserted between the Tcl commands
that open and close the project.
If you select Custom and want to generate a
bitstream, the bitstream generation Tcl command must refer to the top
file wrapper name and location either directly or implicitly. For
example, the following Xilinx
Vivado Tcl command generates a bitstream and implicitly refers to
the top file name and
location:
launch_runs impl_1 -to_step write_bitstream
Program the connected target SoC device. Specify the Programming method for the target device:
JTAG: Uses a JTAG cable to program the
target SoC device.
Download: This is the default
Programming method. Copies the generated FPGA
bistream, device tree, and system initialization scripts to the SD card
on the Zynq board, and keeps the bitstream on the SD card persistently.
To use this programming method, you do not require an Embedded Coder license. You can create an SSH object by specifying the
IP Address, SSH Username,
and SSH Password. HDL Coder uses the SSH object to copy the bitstream to the SD card
and reprogram the board.
To define your own function to program the target device in your custom reference
design, you can use the Custom
Programming method. To use the custom programming, register the
function handle of the custom programming function using the
CallbackCustomProgrammingMethod method of the
hdlcoder.ReferenceDesign class. For
example:
hRD.CallbackCustomProgrammingMethod = ...
@parameter_callback.callback_CustomProgrammingMethod;For more information, see Program Target FPGA Boards or SoC Devices.