The HDL Coder™ software creates and displays an HTML code generation report when you select one or more of the following options. You can specify the UI options in the HDL Code Generation > Report pane of the Configuration Parameters dialog box.
| GUI option | makehdl Property | Dependency |
|---|---|---|
| Generate traceability report | Traceability | Generate HDL code must be enabled. |
| Generate resource utilization report | ResourceReport | Generate HDL code and Generated model must be enabled. |
| Generate high-level timing critical path report | CriticalPathEstimation | Generate HDL code and Generated model must be enabled. |
| Generate optimization report | OptimizationReport | Generate HDL code and Generated model must be enabled. |
| Generate model Web view | HDLGenerateWebview | Generate HDL code must be enabled. |
When you generate code, the Code Generation Report appears in a separate window.
The Code Generation Report is an HTML file that includes a Summary, a Clock Summary, a Code Interface Report, and one or more of the following optional sections:
Traceability report
Resource utilization report
High-level timing critical path report
Optimization report
Model web view
The Summary lists information about the model, the DUT, the date of code generation, and top-level coder settings. The Summary also lists model properties that have nondefault values.
The Code Interface Report shows the DUT input and output port names, data types, and bit widths. The report displays links corresponding to each input port and output port in your Simulink® model.
When you select Generate resource utilization report, HDL Coder adds a Timing and Area Report section to the Code Generation Report. This section of the report contains the following subsections:
High-level Resource Report: This section The Summary section summarizes multipliers, adders/subtractors, and registers consumed by the device under test (DUT).
The Detailed Report section contains more information on the resources that each subsystem uses. Wherever possible, the detailed report links back to corresponding blocks in your model. The Detailed Report section also contains a Registers section. This section displays the total 1-bit registers that is calculated as the sum of products over the bit widths of the registers and their frequency of occurrence.
Target-Specific Report: When you request target-specific code generation on the model, this subsection shows the resource utilization report.
When you select Generate optimization report, HDL Coder adds an Optimization Report section, with three subsections:
Distributed Pipelining: If a subsystem has the
DistributedPipelining option enabled, this
subsection displays comparative listings of registers before and after you
apply the distributed pipelining transform.
Streaming and Sharing: Summary and detailed information about the subsystems for which you specify sharing or streaming optimizations and the delay balancing summary.
Target Code Generation: Summary, status, and path delay information about the subsystems after target code generation.
Delay Balancing: Lists the number of pipeline delays and phase delays added at the output ports to match the delays.