Model Design and Software Interface

Model algorithm to map DUT ports to AXI interfaces and generate software interface to probe and rapidly prototype HDL IP core

When you partition your design into hardware and software components, use the HDL Coder™ HDL Workflow Advisor to target your design on standalone FPGA boards, SoC devices, and Speedgoat FPGA IO modules. The design consists of the DUT algorithm for which you generate the RTL code and IP core. You can integrate the IP core into a reference design for the target platform. To test the HDL IP core functionality, you can use a generated software interface model or a software interface script.

Classes

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hdlcoder.BoardBoard registration object that describes SoC custom board
hdlcoder.ReferenceDesignReference design registration object that describes SoC reference design
fpgaAccess target FPGA or SoC device from MATLAB
hdlcoder.DUTPortDUT port from an HDL Coder generated IP core, saved as an object array

Functions

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addAXI4MasterInterfaceAdd and define AXI4 Master interface
addAXI4SlaveInterfaceAdd and define AXI4 slave interface
addAXI4StreamInterfaceAdd AXI4-Stream interface
addAXI4StreamVideoInterfaceAdd AXI4-Stream Video interface
addAXI4SlaveInterfaceWrite data to IP core or read data from IP core using AXI4 or AXI4-Lite interface
addAXI4StreamInterfaceWrite data to IP core or read data from IP core using AXI4-Stream interface
mapPortMaps a DUT port to specified AXI4 interface in HDL IP core
writePortWrite data to a DUT port from MATLAB
readPortReads output data and returns it with the port data type and dimension
releaseRelease the hardware resources associated with the fpga object

Topics

Modeling for AXI Interfaces

Model Design for AXI4 Slave Interface Generation

How to design your model for AXI4 or AXI4-Lite interfaces for scalar or vector ports and read back values.

Model Design for AXI4-Stream Interface Generation

How to design your model for AXI4-Stream vector or scalar interface generation.

Model Design for AXI4-Stream Video Interface Generation

How to design your model for IP core generation with AXI4-stream video interfaces.

Model Design for AXI4 Master Interface Generation

Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.

Software Interface Generation

Generate Software Interface to Probe and Rapidly Prototype the HDL IP Core

Generate software interface model or software interface script to communicate with the HDL IP core and perform rapid prototyping.

Create Software Interface Script to Control and Rapidly Prototype HDL IP Core

Create fpga object and author software interface script by configuring interfaces and port mapping information to control HDL IP core.

Featured Examples

Getting Started with Targeting Intel SoC Devices

Getting Started with Targeting Intel SoC Devices

Use the hardware-software co-design workflow to blink LEDs at various frequencies on the Arrow® SoCKit® evaluation kit.

Open Script
Getting Started with AXI4-Stream Interface in Zynq Workflow

Getting Started with AXI4-Stream Interface in Zynq Workflow

Use the AXI4-Stream interface to enable high speed data transfer between the processor and FPGA on Zynq hardware.

Open Script
Getting Started with AXI4-Stream Video Interface in Zynq Workflow

Getting Started with AXI4-Stream Video Interface in Zynq Workflow

Use the AXI4-Stream Video interface to enable high speed video streaming on the generated HDL IP core.

Open Script
Performing Large Matrix Operation on FPGA using External Memory

Performing Large Matrix Operation on FPGA using External Memory

Generate an HDL IP core with AXI4 Master interface, perform matrix multiplication in HDL IP core, and write output result to DDR memory.

Open Script

HDL Coder Documentation

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