Class: hdlcoder.ReferenceDesign
Package: hdlcoder
Add and define AXI4 slave interface
addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr)
addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,'MasterAddressSpace',master_addr_space)
addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,Name,Value)
addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,'MasterAddressSpace',master_addr_space,Name,Value)
addAXI4SlaveInterface('InterfaceConnection', adds
and defines an AXI4 interface for an Altera® reference design,
or an AXI4 or AXI4-Lite interface for a Xilinx® ISE reference
design.ref_design_port,'BaseAddress',base_addr)
addAXI4SlaveInterface('InterfaceConnection', adds
and defines an AXI4 or AXI4-Lite interface for Xilinx Vivado® reference
designs.ref_design_port,'BaseAddress',base_addr,'MasterAddressSpace',master_addr_space)
addAXI4SlaveInterface('InterfaceConnection', adds
and defines an AXI4 interface for an Altera reference design,
or an AXI4 or AXI4-Lite interface for a Xilinx ISE reference
design, with additional options specified by one or more ref_design_port,'BaseAddress',base_addr,Name,Value)Name,Value pair
arguments.
addAXI4SlaveInterface('InterfaceConnection', adds
and defines an AXI4 or AXI4-Lite interface for Xilinx Vivado reference
designs, with additional options specified by one or more ref_design_port,'BaseAddress',base_addr,'MasterAddressSpace',master_addr_space,Name,Value)Name,Value pair
arguments.
Specify optional
comma-separated pairs of Name,Value arguments. Name is
the argument name and Value is the corresponding value.
Name must appear inside quotes. You can specify several name and value
pair arguments in any order as
Name1,Value1,...,NameN,ValueN.
InterfaceType — Interface type{'AXI4-Lite','AXI4'} (default) | 'AXI4' | 'AXI4-Lite'Type of interface connection, specified as a character
vector or a cell array of character vectors.
Example: 'InterfaceType','AXI4-Lite' specifies
an 'AXI4–Lite' interface type
connection.
InterfaceID — Interface name{'AXI4-Lite','AXI4'} (default) | character vectorName of the interface, specified as a character vector. When
you provide the InterfaceID, InterfaceType must
be set to either 'AXI4' or 'AXI4–Lite'.
Example: 'InterfaceID','MyAXI4','InterfaceType','AXI4' specifies
interface name as 'MyAXI4' and interface type as 'AXI4'.
IDWidth — Width of ID signals12 (default) | positive integerWidth of all ID signals, such as
AWID, WID,
ARID, and RID, specified as a positive
integer. This property enables you to specify the number of AXI Master
interfaces that you want the AXI4 slave interface in the HDL DUT IP core to
connect to. The default value is 12, which enables you to
connect the HDL IP core to one AXI Master interface. To connect the IP core
to multiple AXI Master interfaces, increase the
IDWidth. The ID width is tool-specific.
Example: 'IDWidth','13' may indicate that you want the
IP core to connect to two AXI Master interfaces in the reference
design.
Before running this method, you must run the addClockInterface method.
The addAXI4SlaveInterface method
is optional. You can define your own custom reference design without
the AXI4 slave interface.
To connect the HDL IP core for your DUT to multiple AXI Master interfaces in
the reference design, use the IDWidth property of this
method. To learn more, see Define Multiple AXI Master Interfaces in Reference Designs to access DUT AXI4 Slave Interface.
addClockInterface | hdlcoder.ReferenceDesign