Hardware Software Co-Design Basics
When you partition your design into hardware and software components, use the HDL Coder™ HDL Workflow Advisor to target your design on standalone FPGA boards, SoC devices, and Speedgoat FPGA IO modules. The design consists of the DUT algorithm for which you generate the RTL code and IP core, and software components for which you generate embedded code to run on the processor. You use AXI interfaces to interface between the hardware and software components.
Classes
Topics
Hardware-Software Co-Design Workflow for SoC Platforms
High-level workflow steps for targeting an SoC platform.
Processor and FPGA Synchronization
In the HDL Workflow Advisor, you can choose a Processor/FPGA synchronization mode for your processor and FPGA when you:The following synchronization modes are available:
Run HDL Workflow with a Script
Export, import, or configure an HDL Workflow CLI command script.
Getting Started with the HDL Workflow Advisor
Learn the basics of the HDL Workflow Advisor and how to run various tasks.
Model and Debug Test Point Signals with HDL Coder
An example that shows how to add test points to signals in your model and debug these signals in the generated HDL code.
Program Target FPGA Boards or SoC Devices
How to program the target Intel or Xilinx Hardware.
